CMOS tree decoder with speed enhancement by adjustment of gate width

Claim 1

A semiconductor decoder circuit comprising: 2 N-1 number of NAND gate means, each having N inputs and collectively developing an output, where N is greater than 2, each said NAND gate means including; N first transistors, each having a control terminal coupled to receive one of said N inputs and first and second controlled terminals, said first controlled terminals being commonly connected together to said output, said second controlled terminals coupled to receive a supply voltage; and a unique path of at least N-1 second transistors, said second transistors each having an input gate coupled to receive one of said N inputs and third and fourth controlled terminals, said N-1 second transistors in said unique path being serially connected together by their respective third and fourth terminals to form N-1 stages between said commonly connected first controlled terminals and a reference node; said unique path between each of said 2 N-1 number of NAND gate means and said reference node sharing at least some of said N-1 second transistors with the unique path of others of said NAND gate means, said N-1 second transistors of all of said 2 N-1 number of NAND gate means being connected in a cascade arrangement with said said unique paths intersecting to connect the N first transistors of each of said 2 N-1 number of NAND gate means to said reference node at a single point; each gate of one of said N-1 second transistors in the N-1 stage having a gate width inversely proportional to the number of transistors in said N-1 stage to thereby make the total gate width of all of said second transistors at each said stage substantially constant.