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US4491839A Expired / Lapsed US ⏱️ 0.0 years remaining

CMOS Selection circuit

Assignee: ITT Inc
•
Filing: 1982-04-30
•
Granted: 1985-01-01
•
Expires: 2002-04-30
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Abstract

Abstract In a circuit for selecting a random number (N) of potentials (Ui . . . ), which is integrated in accordance with the complementary insulated-gate field-effect transistor technique, one transmission gate (G . . . ) is associated with each potential, with the switching section of the gate lying between the potential (Ui . . . ) and the output (U), and the two control inputs of the respective transmission gate (G . . . ) are connected either directly or via a respectively associated inverter (I . . . ) to the corresponding output of a CMOS-1-ex-n-decoder. This decoder may consist of a 1-ex-n-open-circuit-decoder (SD) and of a 1-ex-n-short-circuit decoder (KD) whose address inputs are connected in pairs to one another and whose like outputs (1 . . . 8) are connected to one another. The open-circuit decoder (SD) consists of transistors (TP) of the one channel conductivity type, and the short-circuit decoder (KD) consists of transistors (TN) of the other channel conductivity type.

Inventors

  • 👤 Fritz G. Adam

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 06:12
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/693; H03M; H03M7/00; H03M7/001; H03M7/005

Claims Analysis

Total Claims: 21
Claim 1
Independent Claim 117 words
An integrated selection circuit for a number (N) of potentials (Ui . . . ), which is integrated in a complementary insulated-gate field-effect transistor technique (CMOS selection circuit), comprising: at least one transmission gate (G . . . ) assigned to each of the N potentials (U . . . ) whose switching section lies between the potential (U . . . ) and the output (U) of the selection circuit, at least one transmission gate further comprising two control inputs, the two control inputs of the respective transmission gate (G . . . ) being connected either directly or via a respectively associated inverter (I . . . ) to the corresponding output of a CMOS-1-ex-n-decoder.
Claim 2
Dependent Claim 117 words
An integrated selection circuit for a number (N) of potentials (Ui . . . ), which is integrated in a complementary insulated-gate field-effect transistor technique (CMOS selection circuit), comprising: at least one transmission gate (G . . . ) assigned to each of the N potentials (U . . . ) whose switching section lies between the potential (U . . . ) and the output (U) of the selection circuit, at least one transmission gate further comprising two control inputs, the two control inputs of the respective transmission gate (G . . . ) being connected either directly or via a respectively associated inverter (I . . . ) to the corresponding output of a CMOS-1-ex-n-decoder.
Claim 3
Dependent Claim 111 words
A selection circuit as claimed in claim 1 wherein, said CMOS-1-ex-n-decoder comprises a 1-ex-n-open-circuit decoder (SD) and a 1-ex-n-short-circuit decoder (KD) whose address inputs are connected in pairs to one another and whose like outputs (1 . . . 8) are connected to one another, said open-circuit decoder (SD) comprising transistors (TP) of the one channel conductivity type (p-channel in the drawings) which are arranged in an insulating island (NW) of the other channel conductivity type (n-channel in the drawings) within the semiconductor body of the integrated selection circuit, and said short-circuit decoder (KD) comprising transistors (TN) of the other channel conductivity type, which are arranged within the semiconductor body (HK).
Claim 4
Dependent Claim 23 words
A selection circuit as claimed in claim 2, wherein said 1-ex-n-open-circuit or short-circuit decoders are such ones for naturally binary encoded address signals.
Claim 5
Dependent Claim 78 words
A selection circuit as claimed in claims 1, 2 or 3, wherein only those partial transistors (P . . . , N . . . ) of said transmission gates (G . . . ) and those of the inverters (I . . . ) associated with said partial transistors, are provided, with which the associated potential (U . . . ) is capable of being connected through to the output quicker and in a more low-ohmic manner.
Claim 6
Dependent Claim 148 words
A selection circuit as claimed in claim 4, for four potentials to be connected through (U0, U1, U2, U3) of which one (U0) is that of the zero point of the circuit, wherein, to the potential (U0) of the zero point of the circuit as connected through to the output, there belong the selecting signal state 00 and one partial transistor (N0) of the other channel conductivity type having its source and substrate connected thereto, with the gate thereof being connected via the associated inverter (I0) to the corresponding output of the 1-ex-4-binary decoder, and to the other three potentials (U1, U2, U3) there each time belongs one partial transistor (P1, P2, P3) of the one channel conductivity type with respectively one insulating island of its own, of the other channel conductivity type, which is connected to the associated source and to the associated potential (U1, U2, U3).
Claim 7
Dependent Claim 24 words
A selection circuit as claimed in claim 1, wherein one of said potentials is identical to the operating voltage (Ud) of said selection circuit.
Claim 8
Dependent Claim 31 words
A selection circuit as claimed in claim 5, wherein said transistor (P3) as associated with said operating voltage (Ud) is arranged in the insulating island (NW) of said open-circuit decoder (SD).
Claim 9
Dependent Claim 47 words
A selection circuit as claimed in claim 1, wherein the transistors of the one channel conductivity type as lying between the potentials to be selected (Uni) and the output (U), are each time arranged individually in their own respective insulating island of the other channel conductivity type.
Claim 10
Dependent Claim 24 words
A selection circuit as claimed in claim 2, wherein one of said potentials is identical to the operating voltage (Ud) of said selection circuit.
Claim 11
Dependent Claim 24 words
A selection circuit as claimed in claim 3, wherein one of said potentials is identical to the operating voltage (Ud) of said selection circuit.
Claim 12
Dependent Claim 24 words
A selection circuit as claimed in claim 4, wherein one of said potentials is identical to the operating voltage (Ud) of said selection circuit.
Claim 13
Dependent Claim 24 words
A selection circuit as claimed in claim 5, wherein one of said potentials is identical to the operating voltage (Ud) of said selection circuit.
Claim 14
Dependent Claim 30 words
A selection circuit as claimed in claim 9, wherein said transistor (P3) as associated with said operating voltage (Ud) is arranged in the insulating (NW) of said open-circuit decoder (SD).
Claim 15
Dependent Claim 31 words
A selection circuit as claimed in claim 10, wherein said transistor (P3) as associated with said operating voltage (Ud) is arranged in the insulating island (NW) of said open-circuit decoder (SD).
Claim 16
Dependent Claim 31 words
A selection circuit as claimed in claim 11, wherein said transistor (P3) as associated with said operating voltage (Ud) is arranged in the insulating island (NW) of said open-circuit decoder (SD).
Claim 17
Dependent Claim 31 words
A selection circuit as claimed in claim 12, wherein said transistor (P3) as associated with said operating voltage (Ud) is arranged in the insulating island (NW) of said open-circuit decoder (SD).
Claim 18
Dependent Claim 47 words
A selection circuit as claimed in claim 2, wherein the transistors of the one channel conductivity type as lying between the potentials to be selected (Uni) and the output (U), are each time arranged individually in their own respective insulating island of the other channel conductivity type.
Claim 19
Dependent Claim 47 words
A selection circuit as claimed in claim 3, wherein the transistors of the one channel conductivity type as lying between the potentials to be selected (Uni) and the output (U), are each time arranged individually in their own respective insulating island of the other channel conductivity type.
Claim 20
Dependent Claim 47 words
A selection circuit as claimed in claim 4, wherein the transistors of the one channel conductivity type as lying between the potentials to be selected (Uni) and the output (U), are each time arranged individually in their own respective insulating island of the other channel conductivity type.
Claim 21
Dependent Claim 47 words
A selection circuit as claimed in claim 5, wherein the transistors of the one channel conductivity type as lying between the potentials to be selected (Uni) and the output (U), are each time arranged individually in their own respective insulating island of the other channel conductivity type.

References Cited (Backward Citations)

US4091293A Cited
US4424460A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-01-01 1988-07-02 1989-01-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-01-01 1992-07-02 1993-01-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-01-01 1996-07-02 1997-01-01 $7700.00 Window Closed / Lapsed

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