US4620117A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Balanced CMOS logic circuits
Assignee: Advanced Micro Devices Inc
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Filing: 1985-01-04
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Granted: 1986-10-28
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Expires: 2005-01-04
Abstract
Abstract A logic gate circuit composed of CMOS transistors includes at least a first pair of transistors formed of first and second transistors of one conductivity type having gate, source and drain electrodes. The logic gate circuit further includes at least a second pair of transistors formed of third and fourth transistors of the same conductivity as the first pair and having gate, source and drain electrodes. The source and drain electrodes of the first and second pairs are adapted to receive input signals. A pair of cross-coupled transistors formed of fifth and sixth transistors of a complementary electrodes are provided. The gate of the fifth transistor is connected to the drain of the sixth transistor, and the gate of the sixth transistor is connected to the drain of the fifth transistor. The drain of the fifth transistor is further connected to the drains of the first and second transistors and to a true output terminal. The drain of the sixth transistor is further connected to the drains of the third and fourth transistors and to a complement output terminal. All of the first through sixth transistors are arranged on an integrated circuit substrate with topological regularity.
Inventors
- 👤 Sheng Fang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:12
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/21; H03K19/215; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
338 words
A balanced CMOS AND logic gate circuit comprising: a first pair of N-channel type MOS transistors formed of first and second transistors whose drains are connected together; a second pair of N-channel type MOS transistors formed of third and fourth transistors whose drains are connected together; a third pair of N-channel type MOS transistors formed of fifth and sixth transistors whose drains are connected together; a fourth pair of N-channel type MOS transistors formed of seventh and eighth transistors whose drains are connected together; a supply potential being connected to the sources of said first, fourth and eighth transistors; a ground potential being connected to the sources of said second, third and sixth transistors; the source of said fifth transistor being connected to the drains of said first and second transistors; the source of said seventh transistor being connected to the drains of said third and fourth transistors; a first true input signal being applied via a first input terminal to the gates of the first and third transistors; a complement of said first input signal being applied via a second input terminal to the gates of said second and fourth transistors; a second true input signal being applied via a third input terminal to the gates of said fifth and seventh transistors; a complement of said second input signal being applied via a fourth input terminal to the gates of said sixth and eighth transistors; a pair of cross-coupled P-channel type MOS transistors formed of ninth and tenth transistors whose sources are coupled to the supply potential, the gate of said ninth transistor being connected to the drain of said tenth transistor and the gate of said tenth transistor being connected to the drain of said ninth transistor; the drain of said ninth transistor being further connected to the drains of said fifth and sixth transistors and to a true output terminal; and the drain of said tenth transistor being further connected to the drains of said seventh and eighth transistors and to a complement output terminal.
Claim 2
Dependent Claim
338 words
A balanced CMOS AND logic gate circuit comprising: a first pair of N-channel type MOS transistors formed of first and second transistors whose drains are connected together; a second pair of N-channel type MOS transistors formed of third and fourth transistors whose drains are connected together; a third pair of N-channel type MOS transistors formed of fifth and sixth transistors whose drains are connected together; a fourth pair of N-channel type MOS transistors formed of seventh and eighth transistors whose drains are connected together; a supply potential being connected to the sources of said first, fourth and eighth transistors; a ground potential being connected to the sources of said second, third and sixth transistors; the source of said fifth transistor being connected to the drains of said first and second transistors; the source of said seventh transistor being connected to the drains of said third and fourth transistors; a first true input signal being applied via a first input terminal to the gates of the first and third transistors; a complement of said first input signal being applied via a second input terminal to the gates of said second and fourth transistors; a second true input signal being applied via a third input terminal to the gates of said fifth and seventh transistors; a complement of said second input signal being applied via a fourth input terminal to the gates of said sixth and eighth transistors; a pair of cross-coupled P-channel type MOS transistors formed of ninth and tenth transistors whose sources are coupled to the supply potential, the gate of said ninth transistor being connected to the drain of said tenth transistor and the gate of said tenth transistor being connected to the drain of said ninth transistor; the drain of said ninth transistor being further connected to the drains of said fifth and sixth transistors and to a true output terminal; and the drain of said tenth transistor being further connected to the drains of said seventh and eighth transistors and to a complement output terminal.
Claim 3
Dependent Claim
28 words
A logic gate as claimed in claim 1, wherein true and complement output signals are generated at the respective true and complement output terminals at the same time.
Claim 4
Dependent Claim
33 words
A logic gate circuit as claimed in claim 1, wherein all of said first through tenth transistors are arranged on an integrated circuit substrate with topological regularity so as to simplify their layout.
Claim 5
Dependent Claim
258 words
A balanced CMOS AND logic gate circuit comprising: a first pair of N-channel type MOS transistors formed of first and second transistors whose drains are connected together; a second pair of N-channel type MOS transistors formed of third and fourth MOS transistors whose drains are connected together; a supply potential being connected to the source of said fourth transistor; a ground potential being connected to the source of said second transistor; a first true input signal being applied via a first input terminal to the source of said first transistor; a complement of said first input signal being applied via a second input terminal to the source of said third transistor; a second true input signal being applied via a third input terminal to the gates of said first and third transistors; a second complement of said second input signal being applied via a fourth input terminal to the gates of said second and fourth transistors; a pair of cross-coupled P-channel type MOS transistors formed of fifth and sixth transistors whose sources are coupled to the supply potential, the gate of said fifth transistor being connected to the drain of said sixth transistor and the gate of said sixth transistor being connected to the drain of said fifth transistor; the drain of said fifth transistor being further connected to the drains of said first and second transistors and to a true output terminal; and the drain of said sixth transistor being further connected to the drains of said third and fourth transistors and to a complement output terminal.
Claim 6
Dependent Claim
258 words
A balanced CMOS AND logic gate circuit comprising: a first pair of N-channel type MOS transistors formed of first and second transistors whose drains are connected together; a second pair of N-channel type MOS transistors formed of third and fourth MOS transistors whose drains are connected together; a supply potential being connected to the source of said fourth transistor; a ground potential being connected to the source of said second transistor; a first true input signal being applied via a first input terminal to the source of said first transistor; a complement of said first input signal being applied via a second input terminal to the source of said third transistor; a second true input signal being applied via a third input terminal to the gates of said first and third transistors; a second complement of said second input signal being applied via a fourth input terminal to the gates of said second and fourth transistors; a pair of cross-coupled P-channel type MOS transistors formed of fifth and sixth transistors whose sources are coupled to the supply potential, the gate of said fifth transistor being connected to the drain of said sixth transistor and the gate of said sixth transistor being connected to the drain of said fifth transistor; the drain of said fifth transistor being further connected to the drains of said first and second transistors and to a true output terminal; and the drain of said sixth transistor being further connected to the drains of said third and fourth transistors and to a complement output terminal.
Claim 7
Dependent Claim
29 words
A logic gate circuit as claimed in claim 4, wherein true and complement output signals are generated at the respective true and complement output terminals at the same time.
Claim 8
Dependent Claim
33 words
A logic gate circuit as claimed in claim 4, wherein all of said first through sixth transistors are arranged on an integrated circuit substrate with topological regularity so as to simplify their layout.
Claim 9
Dependent Claim
244 words
A logic gate circuit composed of CMOS transistors comprising: a first pair of transistors formed of first and second transistors of one conductivity type having gate, source and drain electrodes; a second pair of transistors formed of third and fourth transistors of the same conductivity type as said first pair and having gate, source and drain electrodes; a supply potential being connected to the sources of said first and third transistors; a ground potential being connected to the sources of said second and fourth transistors; an input signal being applied via a first input terminal to the gates of said first and fourth transistors; a complement of said input signal being applied via a second input terminal to the gates of said second and third transistors; a first pair of cross-coupled transistors formed of fifth and sixth transistors of a complementary conductivity type and having gate, source and drain electrodes, the gate of said fifth transistor being connected to the drain of said sixth transistor and the gate of the sixth transistor being connected to the drain of said fifth transistor; the sources of said fifth and sixth transistor being coupled to the supply potential; the drain of said fifth transistor being further connected to the drains of said first and second transistors and to a true output terminal; and the drain of said sixth transistor being further connected to the drains of said third and fourth transistors and to a complement output terminal.
Claim 10
Dependent Claim
244 words
A logic gate circuit composed of CMOS transistors comprising: a first pair of transistors formed of first and second transistors of one conductivity type having gate, source and drain electrodes; a second pair of transistors formed of third and fourth transistors of the same conductivity type as said first pair and having gate, source and drain electrodes; a supply potential being connected to the sources of said first and third transistors; a ground potential being connected to the sources of said second and fourth transistors; an input signal being applied via a first input terminal to the gates of said first and fourth transistors; a complement of said input signal being applied via a second input terminal to the gates of said second and third transistors; a first pair of cross-coupled transistors formed of fifth and sixth transistors of a complementary conductivity type and having gate, source and drain electrodes, the gate of said fifth transistor being connected to the drain of said sixth transistor and the gate of the sixth transistor being connected to the drain of said fifth transistor; the sources of said fifth and sixth transistor being coupled to the supply potential; the drain of said fifth transistor being further connected to the drains of said first and second transistors and to a true output terminal; and the drain of said sixth transistor being further connected to the drains of said third and fourth transistors and to a complement output terminal.
Claim 11
Dependent Claim
31 words
A logic gate circuit as claimed in claim 7, wherein said first through fourth transistors are N-channel type MOS transistors and said fifth and sixth transistors are P-channel type MOS transistors.
Claim 12
Dependent Claim
29 words
A logic gate circuit as claimed in claim 7, wherein true and complement output signals are generated at the respective true and complement output terminals at the same time.
Claim 13
Dependent Claim
32 words
A logic circuit as claimed in claim 7, wherein all of said first through sixth transistors are arranged on an integrated circuit substrate with topological regularity so as to simplify their layout.
References Cited (Backward Citations)
US4350905A
Cited
US4367420A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-27 | 1990-04-28 | 1990-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-27 | 1994-04-28 | 1994-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-27 | 1998-04-28 | 1998-10-28 | $7700.00 | Window Closed / Lapsed |