US4367420A
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US
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Dynamic logic circuits operating in a differential mode for array processing
Assignee: THOMPSON FOSS Inc
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Filing: 1980-06-02
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Granted: 1983-01-04
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Expires: 2000-06-02
Abstract
Abstract The disclosure teaches various logic circuits operating with Dynamic Differential Logic (DDL). In a particular embodiment MOS transistors of n-channel type are used with circuits arranged to avoid any dc path from clock input to ground. The input capacitance of the active devices is used for temporary storage thereby reducing circuit complexities. Coupling between stages is provided by clock driven transistors connected so that the transistor at the higher voltage side cuts off early in the period of clock pulse decay, thereby isolating adjacent stages without unnecessary delay. The use of such circuits in array processors is described.
Inventors
- 👤 Richard C. Foss
- 👤 Philip M. Thompson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:27
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
161 words
A logic circuit formed from input-controlled active devices having inherent reactive storage, comprising: a first pair of devices, each having an input reactance, connected as a cross-connection regenerative circuit, one of said first pair of devices having a first array of devices performing a first logic function connected between said one of said first pair of devices and a source of clock pulses, and the other of said first pair of devices having a corresponding second array of devices performing a second logic function complementary to the first logic function and connected between said other of said first pair of devices and the source of clock pulses, each of said arrays of devices having inputs for receiving input signals from a set of differential logic signals; and a second pair of devices connected to the source of clock pulses for selectively isolating or coupling the voltage levels across the input reactances of said first pair of devices to subsequent logic stages.
Claim 2
Dependent Claim
161 words
A logic circuit formed from input-controlled active devices having inherent reactive storage, comprising: a first pair of devices, each having an input reactance, connected as a cross-connection regenerative circuit, one of said first pair of devices having a first array of devices performing a first logic function connected between said one of said first pair of devices and a source of clock pulses, and the other of said first pair of devices having a corresponding second array of devices performing a second logic function complementary to the first logic function and connected between said other of said first pair of devices and the source of clock pulses, each of said arrays of devices having inputs for receiving input signals from a set of differential logic signals; and a second pair of devices connected to the source of clock pulses for selectively isolating or coupling the voltage levels across the input reactances of said first pair of devices to subsequent logic stages.
Claim 3
Dependent Claim
27 words
A logic circuit as set out in claim 1, wherein the inputs to said arrays of devices are arranged for the circuit to function as a multiplexer.
Claim 4
Dependent Claim
75 words
A logic circuit as set out in claim 1 wherein said logic circuit is connected to function as a fast carry gate for use in an adder or multiplier system having two coefficients to be added and a carry signal, wherein said first array has a first input connected to the carry signal, a second input connected to one of the coefficients, and a control input connected to an exclusive OR combination of the coefficients.
Claim 5
Dependent Claim
194 words
A logic circuit formed from input-controlled active devices having inherent reactive storage, comprising: a first pair of devices, each having an input reactance, connected as a cross-connection regenerative circuit, one of said first pair of devices having a first array of devices performing a first logic function connected between said one of said first pair of devices and a source of clock pulses, and the other of said first pair of devices having a corresponding second array of devices performing a second logic function complementary to the first logic function and connected between said other of said first pair of devices and the source of clock pulses, each of said arrays of devices having inputs for receiving input signals from a set of differential logic signals; and a second pair of devices connected to the source of clock pulses for selectively isolating or coupling the voltage levels across the input reactances of said first pair of devices to subsequent logic stages; wherein said first array comprises an AND array, and said corresponding second array comprises an OR array, thereby forming an AND gate with a NAND output available from the other of said devices.
Claim 6
Dependent Claim
194 words
A logic circuit formed from input-controlled active devices having inherent reactive storage, comprising: a first pair of devices, each having an input reactance, connected as a cross-connection regenerative circuit, one of said first pair of devices having a first array of devices performing a first logic function connected between said one of said first pair of devices and a source of clock pulses, and the other of said first pair of devices having a corresponding second array of devices performing a second logic function complementary to the first logic function and connected between said other of said first pair of devices and the source of clock pulses, each of said arrays of devices having inputs for receiving input signals from a set of differential logic signals; and a second pair of devices connected to the source of clock pulses for selectively isolating or coupling the voltage levels across the input reactances of said first pair of devices to subsequent logic stages; wherein said first array comprises an AND array, and said corresponding second array comprises an OR array, thereby forming an AND gate with a NAND output available from the other of said devices.
Claim 7
Dependent Claim
194 words
A logic circuit formed from input-controlled active devices having inherent reactive storage, comprising: a first pair of devices, each having an input reactance, connected as a cross-connection regenerative circuit, one of said first pair of devices having a first array of devices performing a first logic function connected between said one of said first pair of devices and a source of clock pulses, and the other of said first pair of devices having a corresponding second array of devices performing a second logic function complementary to the first logic function and connected between said other of said first pair of devices and the source of clock pulses, each of said arrays of devices having inputs for receiving input signals from a set of differential logic signals; and a second pair of devices connected to the source of clock pulses for selectively isolating or coupling the voltage levels across the input reactances of said first pair of devices to subsequent logic stages; wherein said first array comprises an OR array, and said corresponding second array comprises an AND array, thereby forming an OR gate with a NOR output available from the other of said devices.
Claim 8
Dependent Claim
194 words
A logic circuit formed from input-controlled active devices having inherent reactive storage, comprising: a first pair of devices, each having an input reactance, connected as a cross-connection regenerative circuit, one of said first pair of devices having a first array of devices performing a first logic function connected between said one of said first pair of devices and a source of clock pulses, and the other of said first pair of devices having a corresponding second array of devices performing a second logic function complementary to the first logic function and connected between said other of said first pair of devices and the source of clock pulses, each of said arrays of devices having inputs for receiving input signals from a set of differential logic signals; and a second pair of devices connected to the source of clock pulses for selectively isolating or coupling the voltage levels across the input reactances of said first pair of devices to subsequent logic stages; wherein said first array comprises an OR array, and said corresponding second array comprises an AND array, thereby forming an OR gate with a NOR output available from the other of said devices.
Claim 9
Dependent Claim
180 words
A logic circuit formed from input-controlled active devices having inherent reactive storage, comprising: a first pair of devices, each having an input reactance, connected as a cross-connection regenerative circuit, one of said first pair of devices having a first array of devices performing a first logic function connected between said one of said first pair of devices and a source of clock pulses, and the other of said first pair of devices having a corresponding second array of devices performing a second logic function complementary to the first logic function and connected between said other of said first pair of devices and the source of clock pulses, each of said arrays of devices having inputs for receiving input signals from a set of differential logic signals; and a second pair of devices connected to the source of clock pulses for selectively isolating or coupling the voltage levels across the input reactances of said first pair of devices to subsequent logic stages; wherein said first array is an exclusive OR array and said corresponding second array is an exclusive NOR array.
Claim 10
Dependent Claim
180 words
A logic circuit formed from input-controlled active devices having inherent reactive storage, comprising: a first pair of devices, each having an input reactance, connected as a cross-connection regenerative circuit, one of said first pair of devices having a first array of devices performing a first logic function connected between said one of said first pair of devices and a source of clock pulses, and the other of said first pair of devices having a corresponding second array of devices performing a second logic function complementary to the first logic function and connected between said other of said first pair of devices and the source of clock pulses, each of said arrays of devices having inputs for receiving input signals from a set of differential logic signals; and a second pair of devices connected to the source of clock pulses for selectively isolating or coupling the voltage levels across the input reactances of said first pair of devices to subsequent logic stages; wherein said first array is an exclusive OR array and said corresponding second array is an exclusive NOR array.
Claim 11
Dependent Claim
16 words
A logic circuit as set out in claim 6 wherein said input-controlled active devices are transistors.
Claim 12
Dependent Claim
19 words
A logic circuit as set out in claim 7 wherein said transistors are MOS transistors with inherent electrode capacitance.
Claim 13
Dependent Claim
131 words
A logic stage formed from input-controlled active devices having inherent electrode capacitance, comprising: a first pair of devices connected as a cross-coupled regenerative circuit; each device having a further device connected between it and a source of clock pulses of a first phase, each said further device having an input reactance; and first and second sets of devices performing complementary logic functions energized by a source of clock pulses of a second phase and connected to receive input signals from a set of differential logic signals, each set of devices being connected to a different one of said further devices, whereby one such further device is selectively energized and the input reactance of the further device switched into conduction is much larger than the input reactance of the other further device.
Claim 14
Dependent Claim
131 words
A logic stage formed from input-controlled active devices having inherent electrode capacitance, comprising: a first pair of devices connected as a cross-coupled regenerative circuit; each device having a further device connected between it and a source of clock pulses of a first phase, each said further device having an input reactance; and first and second sets of devices performing complementary logic functions energized by a source of clock pulses of a second phase and connected to receive input signals from a set of differential logic signals, each set of devices being connected to a different one of said further devices, whereby one such further device is selectively energized and the input reactance of the further device switched into conduction is much larger than the input reactance of the other further device.
Claim 15
Dependent Claim
16 words
A logic circuit as set out in claim 9 wherein said input-controlled active devices are transistors.
Claim 16
Dependent Claim
19 words
A logic circuit as set out in claim 10 wherein said transistors are MOS transistors with inherent electrode capacitance.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-01-03 | 1986-07-05 | 1987-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-01-03 | 1990-07-05 | 1991-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-01-03 | 1994-07-05 | 1995-01-04 | $7700.00 | Window Closed / Lapsed |