US4292548A
Expired / Lapsed
US
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Dynamically programmable logic circuits
Assignee: Instituto Venezolano de Investigaciones Científicas
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Filing: 1979-07-27
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Granted: 1981-09-29
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Expires: 1999-07-27
Abstract
Abstract A programmable logic circuit is formed by at least one gate. The gate is formed by four logic circuits, one being a first exclusive NOR circuit having a first input, a second input and an output. A second exclusive NOR circuit having a first input, a second input and output is provided, the first input of the second exclusive NOR circuit being coupled to the first input of said first exclusive NOR circuit. An AND circuit having a first input, a second input and an output is also provided. The first input of the AND circuit is coupled to the output of the first exclusive NOR circuit and the second input of the AND circuit means is coupled to the output of the second exclusive NOR circuit. A third exclusive NOR circuit having a first input circuit, a second input circuit and an output circuit is provided the first input circuit of the third exclusive NOR circuit is coupled to the output of the AND circuit. The gate can selectively function as an OR, NOR, AND and NAND circuit depending on ONE and ZERO signal levels applied to the respective second inputs of the second and the third exclusive NOR circuits as program variables. One of the variables is applied to the first input of the first exclusive NOR circuit and to the first input of the second exclusive NOR circuit, another variable being applied to the first input of the second exclusive NOR circuit. By connecting the second input of the second exclusive NOR circuit to one of the inputs of the first exclusive NOR circuit, the logic circuit will operate as an exclusive OR or exclusive NOR circuit.
Inventors
- 👤 Ricardo Suarez
- 👤 Oscar Chang
- 👤 Vladimir Adam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/20; H03K19/21; H03K19/215
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
257 words
A programmable logic circuit including at least one gate comprising: first exclusive NOR circuit means having first input means, second input means and output means; second exclusive NOR circuit means having first input means, second input means and output means, said first input means of said second exclusive NOR circuit means being coupled to said first input means of said first exclusive NOR circuit means; AND circuit means having first input means, second input means and output means, said first input means of said AND circuit means being coupled to said output means of said first exclusive NOR circuit means and said second input means of said AND circuit means being coupled to said output means of said second exclusive NOR circuit means; and third exclusive NOR circuit means having first input circuit means, second input circuit means and output circuit means, said first input circuit means of said third exclusive NOR circuit means being coupled to said output means of said AND circuit means; whereby the least one gate can selectively function as an OR, NOR, AND and NAND circuit depending on ONE and ZERO signal levels applied to the respective second input means of the second and the third exclusive NOR circuit means as program variables, with one independent variable being applied to the first input means of the first exclusive NOR circuit means and to the first input means of the second exclusive NOR circuit means, and another independent variable being applied to the second input means of the first exclusive NOR circuit means.
Claim 2
Dependent Claim
257 words
A programmable logic circuit including at least one gate comprising: first exclusive NOR circuit means having first input means, second input means and output means; second exclusive NOR circuit means having first input means, second input means and output means, said first input means of said second exclusive NOR circuit means being coupled to said first input means of said first exclusive NOR circuit means; AND circuit means having first input means, second input means and output means, said first input means of said AND circuit means being coupled to said output means of said first exclusive NOR circuit means and said second input means of said AND circuit means being coupled to said output means of said second exclusive NOR circuit means; and third exclusive NOR circuit means having first input circuit means, second input circuit means and output circuit means, said first input circuit means of said third exclusive NOR circuit means being coupled to said output means of said AND circuit means; whereby the least one gate can selectively function as an OR, NOR, AND and NAND circuit depending on ONE and ZERO signal levels applied to the respective second input means of the second and the third exclusive NOR circuit means as program variables, with one independent variable being applied to the first input means of the first exclusive NOR circuit means and to the first input means of the second exclusive NOR circuit means, and another independent variable being applied to the second input means of the first exclusive NOR circuit means.
Claim 3
Dependent Claim
19 words
A programmable logic circuit according to claim 1, wherein the logic circuit is formed as a monolithic, integrated circuit.
Claim 4
Dependent Claim
20 words
A programmable logic circuit according to claim 1, wherein said at least one gate comprises a plurality of said gates.
Claim 5
Dependent Claim
20 words
A programmable logic circuit according to claim 3, wherein said plurality of gates is formed as a monolithic, integrated circuit.
Claim 6
Dependent Claim
47 words
A programmable logic circuit according to claim 3, wherein at least more than one of said gates of said plurality of gates have respective said second input means of their respective said second exclusive NOR circuit means coupled together to receive simultaneously one of the program variables.
Claim 7
Dependent Claim
43 words
A programmable logic circuit according to claim 3, wherein all of said gates of said plurality of gates have respective said second input means of their respective said second exclusive NOR circuit means coupled together to receive simultaneously one of the program variables.
Claim 8
Dependent Claim
47 words
A programmable logic circuit according to claim 3, wherein at least more than one of said gates of said plurality of gates have respective said second input means of their respective said third exclusive NOR circuit means coupled together to receive simultaneously one of the program variables.
Claim 9
Dependent Claim
41 words
A programmable logic circuit according to claim 3, wherein all of said gates of said plurality of gates have respective said second input means of said third exclusive NOR circuit means coupled together to receive simultaneously one of the program variables.
Claim 10
Dependent Claim
86 words
A programmable logic circuit according to claim 3, wherein at least more than one of said gates of said plurality of gates have respective said second input means of their respective said second exclusive NOR circuit means coupled together to receive simultaneously one of the program variables, and wherein at least more than one of said plurality of gates have respective said second input means of their respective said third exclusive NOR circuit means coupled together to receive simultaneously the other one of the program variables.
Claim 11
Dependent Claim
81 words
A programmable logic circuit according to claim 3, wherein all of said gates of said plurality of gates have respective said second input means of their respective said second exclusive NOR circuit means coupled together to receive simultaneously one of the program variables, and wherein all of said gates of said plurality of gates have respective said second input means of their respective said third exclusive NOR circuit means coupled together to receive simultaneously the other one of the programmable variables.
Claim 12
Dependent Claim
75 words
A programmable logic circuit according to claim 1, including means interconnecting said second input means of said second exclusive NOR circuit to said first input means of said first exclusive NOR circuit and to said first input means of said first exclusive OR circuit whereby the gate operates as an exclusive OR circuit or an exclusive NOR circuit depending on the program variable applied to the second input means of said third exclusive NOR circuit.
Claim 13
Dependent Claim
25 words
A programmable logic circuit according to claim 11, wherein said means for interconnecting includes switch means which selectively make and break the interconnection provided thereby.
Claim 14
Dependent Claim
63 words
A programmable logic circuit according to claim 1, including means interconnecting said second input means of said second exclusive NOR circuit to said second input means of said first exclusive NOR circuit whereby the gates operates as an exclusive OR circuit or an exclusive NOR circuit depending on the program variable applied to the second input means of said third exclusive NOR circuit.
Claim 15
Dependent Claim
25 words
A programmable logic circuit according to claim 13, wherein said means for interconnecting includes switch means which selectively make and break the interconnection provided thereby.
Claim 16
Dependent Claim
46 words
A programmable logic circuit according to claim 1, including means for selectively connecting said second input means of said second exclusive NOR circuit means alternatively to said first input means of said first exclusive NOR circuit means and to an independent source of a program variables.
Claim 17
Dependent Claim
46 words
A programmable logic circuit according to claim 1, including means for selectively connecting said second input means of said second exclusive NOR circuit means alternatively to said second input means of said first exclusive NOR circuit means and to an independent source of a program variable.
Claim 18
Dependent Claim
59 words
A programmable logic circuit according to claim 1, including means for selectively connecting one at a time to said first input means of said first exclusive NOR circuit means, said first input means of said second exclusive NOR circuit means and an independent source of program variable to said second input means of said third exclusive NOR circuit means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-28 | 1985-03-30 | 1985-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-28 | 1989-03-30 | 1989-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-28 | 1993-03-30 | 1993-09-29 | $7700.00 | Window Closed / Lapsed |