Programmable latch and other circuits for logic arrays

Claim 1

In a programmable logic array chip comprising at least two arrays and a string of latches in which one of the arrays receives interrogation signals from decoders, feeds the responses thereto to the second array which in turn supplies inputs to the latches which can transfer data bits from one to another, new latches each latch comprising: a bi stable circuit having: two three terminal semiconductor devices each with a control terminal and two controlled terminals with the control terminal of each semiconductor coupled to a controlled terminal of the other three terminal semiconductor device, two load devices each for coupling the controlled terminals of three terminal semiconductor devices in series with a source of potential so that when one of the three terminal semiconductor devices is conducting state the other is in an off state; two, two input AND gates each with its output coupled to a different one of the control terminals of the three terminal semiconductor devices so that application of two inputs to either AND gates will determine which one of the three terminal semiconductor devices is in the off state; data transfer means for coupling the outputs of each of AND gates of each latch to the control terminal of one of the three terminal semiconductor devices of the preceding latch in the string of latches to enable changing of the state of each latch with the information stored in the preceding latch independently of the inputs to the AND gates; and, selective coupling means coupling inputs of the AND gates to different outputs of the second array, the bi stable circuit and clocking pulses in different configurations in different latches in the string whereby the string of latches contains different types of latches.