US4710649A
Expired / Lapsed
US
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Transmission-gate structured logic circuits
Assignee: Micron Technology Inc
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Filing: 1986-04-11
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Granted: 1987-12-01
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Expires: 2006-04-11
Abstract
Abstract Unified CMOS logic circuits are based on a structured implementation of transmission-gates. The basic logic building blocks for AND and OR circuits comprise a plurality of transmission-gates some of which may be simplified to a reduced form of a single pass transistor resulting in fewer transistors for implementing logic functions without loss of logic circuit performance characteristics. Three variable logic functions and higher order logic functions are easily implemented. Generally, the required VLSI chip area is minimized as a result of this structured transmission-gate approach.
Inventors
- 👤 Edward T. Lewis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
370 words
A logic circuit for converting a plurality of input logic signals into an output logic signal representative of a predetermined logical combination of the plurality of input logic signals comprising: a plurality of electronic switch means, each of said switch means having an input terminal, an output terminal, a first control terminal and a second control terminal for coupling or decoupling the input terminal and the output terminal selectively in accordance with a logic state of a signal fed to the first and second control terminals; a first one of said plurality of input logic signals being fed to an input terminal of a first one of said switch means; a second one of said plurality of input logic signals being fed to the first control terminal of said first one of said switch means; a second one of said switch means having an input terminal coupled to the output terminal of said first one of said switch means; a third one of said plurality of input logic signals being fed to the first control terminal of said second one of said switch means; output terminals of a third one and a fourth one of said switch means coupled to the output terminal of said second one of said switch means and to an output of said logic circuit wherein: (i) said second one of said plurality of input logic signals being fed to the first control terminal of said third one of said switch means; (ii) said third one of said plurality of input logic signals being fed to the first control terminal of said fourth one of said switch means; and (iii) the input terminal of said third and fourth switch means being coupled to a signal having a predetermined reference potential representative of one of the logic states ofthe input logic signals; a fourth one of said plurality of input logic signals being fed to the second control terminal of said first switch means and the second control terminal of said third switch menas; and a fifth one of said plurality of input logic signals being fed to the second control terminal of said second switch means and the second control terminal of said fourth switch means.
Claim 2
Dependent Claim
370 words
A logic circuit for converting a plurality of input logic signals into an output logic signal representative of a predetermined logical combination of the plurality of input logic signals comprising: a plurality of electronic switch means, each of said switch means having an input terminal, an output terminal, a first control terminal and a second control terminal for coupling or decoupling the input terminal and the output terminal selectively in accordance with a logic state of a signal fed to the first and second control terminals; a first one of said plurality of input logic signals being fed to an input terminal of a first one of said switch means; a second one of said plurality of input logic signals being fed to the first control terminal of said first one of said switch means; a second one of said switch means having an input terminal coupled to the output terminal of said first one of said switch means; a third one of said plurality of input logic signals being fed to the first control terminal of said second one of said switch means; output terminals of a third one and a fourth one of said switch means coupled to the output terminal of said second one of said switch means and to an output of said logic circuit wherein: (i) said second one of said plurality of input logic signals being fed to the first control terminal of said third one of said switch means; (ii) said third one of said plurality of input logic signals being fed to the first control terminal of said fourth one of said switch means; and (iii) the input terminal of said third and fourth switch means being coupled to a signal having a predetermined reference potential representative of one of the logic states ofthe input logic signals; a fourth one of said plurality of input logic signals being fed to the second control terminal of said first switch means and the second control terminal of said third switch menas; and a fifth one of said plurality of input logic signals being fed to the second control terminal of said second switch means and the second control terminal of said fourth switch means.
Claim 3
Dependent Claim
18 words
The circuit recited in claim 1 wherein: each of said electronic switch means comprises a CMOS transmission gate.
Claim 4
Dependent Claim
17 words
The circuit recited in claim 1 wherein: said logic circuit performs logic operations including an AND function.
Claim 5
Dependent Claim
17 words
The circuit recited in claim 1 wherein: said logic circuit performs logic operations including an OR function.
Claim 6
Dependent Claim
312 words
A logic circuit for converting a plurality of input logic signals into an output logic signal representative of a predetermined logical combination of the plurality of input logic signals comprising: a plurality of switch means, each of said switch means having an input terminal, an output terminal, and at least one control terminal for coupling or deoupling the input terminal and the output terminal selectively in accordance with a logic state of a signal fed to said control terminal; a first one of said plurality of input logic signals being fed to an input terminal of a first one of said switch means; a second one of said plurality of input logic signals being fed to a first control terminal of said first one of said switch means; a second one of said switch means having an input terminal coupled to the output terminal of said first one of said switch means; a third one of said plurality of input logic signals being fed to a first control terminal of said second one of said switch means; wherein: (i) output terminals of a third one and a fourth one of said switch means being coupled to the output termianl of said second one of said switch menas and to an output of said logic circuit, and (ii) the input terminal of said third and fourth switch means being coupled to a signal having a predetermined reference potential representative of one of the logic states of the input logic signals; a fourth one of said plurality of input logic signals being fed to a second control terminal of said first switch means and a control terminal of said third switch means; and a fifth one of said plurality of input logic signals being fed to a second control terminal of said second switch means and a control terminal of said fourth switch means.
Claim 7
Dependent Claim
312 words
A logic circuit for converting a plurality of input logic signals into an output logic signal representative of a predetermined logical combination of the plurality of input logic signals comprising: a plurality of switch means, each of said switch means having an input terminal, an output terminal, and at least one control terminal for coupling or deoupling the input terminal and the output terminal selectively in accordance with a logic state of a signal fed to said control terminal; a first one of said plurality of input logic signals being fed to an input terminal of a first one of said switch means; a second one of said plurality of input logic signals being fed to a first control terminal of said first one of said switch means; a second one of said switch means having an input terminal coupled to the output terminal of said first one of said switch means; a third one of said plurality of input logic signals being fed to a first control terminal of said second one of said switch means; wherein: (i) output terminals of a third one and a fourth one of said switch means being coupled to the output termianl of said second one of said switch menas and to an output of said logic circuit, and (ii) the input terminal of said third and fourth switch means being coupled to a signal having a predetermined reference potential representative of one of the logic states of the input logic signals; a fourth one of said plurality of input logic signals being fed to a second control terminal of said first switch means and a control terminal of said third switch means; and a fifth one of said plurality of input logic signals being fed to a second control terminal of said second switch means and a control terminal of said fourth switch means.
Claim 8
Dependent Claim
16 words
The circuit recited in claim 5 wherein: each of said switch means comprises a CMOS transmission-gate.
Claim 9
Dependent Claim
17 words
The circuit recited in claim 5 wherein: said logic circuit performs logic operations including an AND function.
Claim 10
Dependent Claim
17 words
The circuit recited in claim 5 wherein: said logic circuit performs logic operations including an OR function.
Claim 11
Independent Claim
308 words
The method of converting with a logic circuit a plurality of input logic signals into an output logic signal representative of a predetermined logical combination of the plurality of input logic signals, comprising the steps of: providing a plurality of switch means, each of said switch means having an input terminal, an output terminal and at least one control terminal for coupling or decoupling the input terminal and the output terminal selectively in accordance with a logic state of a signal fed to said control terminal; coupling a first one of said plurality of input logic signals to an input terminal of a first one of said switch means; coupling a second one of said plurality of input logic signals to a first control terminal of said first one of said switch means; coupling an output terminal of said first one of said switch means to an input terminal of a second one of said switch means; coupling a third one of said plurality of input logic signals to a first control terminal of said second one of said switch means; coupling output terminals of a third one and a fourth one of said switch means to the output terminal of said second one of said switch means and to an output of said logic circuit; coupling an input terminal of said third and fourth switch means to a signal having a predetermined reference potential representative of one of the logic states of the input logic signals; coupling a fourth one of said plurality of input logic signals to a second control terminal of said first switch means and a control terminal of said third switch means; and coupling a fifth one of said plurality of input logic signals to a second control terminal of said second switch means and a control terminal of said fourth switch means.
Claim 12
Independent Claim
308 words
The method of converting with a logic circuit a plurality of input logic signals into an output logic signal representative of a predetermined logical combination of the plurality of input logic signals, comprising the steps of: providing a plurality of switch means, each of said switch means having an input terminal, an output terminal and at least one control terminal for coupling or decoupling the input terminal and the output terminal selectively in accordance with a logic state of a signal fed to said control terminal; coupling a first one of said plurality of input logic signals to an input terminal of a first one of said switch means; coupling a second one of said plurality of input logic signals to a first control terminal of said first one of said switch means; coupling an output terminal of said first one of said switch means to an input terminal of a second one of said switch means; coupling a third one of said plurality of input logic signals to a first control terminal of said second one of said switch means; coupling output terminals of a third one and a fourth one of said switch means to the output terminal of said second one of said switch means and to an output of said logic circuit; coupling an input terminal of said third and fourth switch means to a signal having a predetermined reference potential representative of one of the logic states of the input logic signals; coupling a fourth one of said plurality of input logic signals to a second control terminal of said first switch means and a control terminal of said third switch means; and coupling a fifth one of said plurality of input logic signals to a second control terminal of said second switch means and a control terminal of said fourth switch means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-30 | 1991-06-01 | 1991-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-30 | 1995-06-01 | 1995-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-30 | 1999-06-01 | 1999-12-01 | $7700.00 | Window Closed / Lapsed |