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US5338983A Expired / Lapsed US ⏱️ 0.0 years remaining

Application specific exclusive of based logic module architecture for FPGAs

Assignee: Texas Instruments Inc
•
Filing: 1993-12-10
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Granted: 1994-08-16
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Expires: 2013-12-10
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Abstract

Abstract A logic module (20) includes five input terminals (a-e), two output terminals (F1, F2), and control logic (22, 24, 26, 28, 30, 32, 36) for selectively coupling one or more of the input terminals to one of the output terminals. First and second input terminals (a, b) are connected to inputs of a first XOR gate (22); a third input terminal (c) is connected to one input of a multiplexor (24) through an inverter (26); a fourth input terminal (d) is connected to the other input of the multiplexor (24) and to one input of a first NAND gate (28); and a fifth input terminal (e) is connected to one input of a second XOR gate (30) and to one input of a second NAND gate (32). The first XOR gate (22) has its output connected to the other input of the first NAND gate (28) and to the control input of the multiplexor (24). The output of the multiplexor (24) is connected to the other inputs of the second XOR gate (30) and second NAND gate (32). The outputs of the first and second NAND gates (28, 32) are connected to the inputs of a third NAND gate (36). The outputs of the third NAND gate (36) and second XOR gate (30) are the output terminals (F2, F1) of the logic module (10). The configuration of the logic module (20) permits implementation of adders and subtractors for DSPs with only one logic module.

Inventors

  • 👤 Manisha Agarwala

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 12:00
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4812

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 31 words
A logic module, comprising: five input terminals; two or more output terminals; and control logic for selectively coupling one or more of the input terminals to one of the output terminals.
Claim 2
Dependent Claim 31 words
A logic module, comprising: five input terminals; two or more output terminals; and control logic for selectively coupling one or more of the input terminals to one of the output terminals.
Claim 3
Dependent Claim 14 words
The logic module of claim 1, wherein the number of output terminals is two.
Claim 4
Dependent Claim 20 words
The logic module of claim 1, wherein the control logic comprises: a plurality of interconnected exclusive-or and Nand logic gates.
Claim 5
Dependent Claim 22 words
The logic module of claim 1, wherein two of said input terminals are connected to the inputs of an exclusive-or logic gate.
Claim 6
Dependent Claim 27 words
The logic module of claim 1, wherein one of said input terminals is connected to one input of multiplexer and to one input of a Nand gate.
Claim 7
Dependent Claim 17 words
The logic module of claim 1, wherein one of said input terminals is connected to an inverter.
Claim 8
Dependent Claim 20 words
The logic module of claim 6, wherein the output of the inverter is connected to one input of a multiplexer.
Claim 9
Dependent Claim 33 words
The logic module of claim 1, wherein one of said input terminals is connected to one input of an XOR logic gate, the output of said gate forming one of said output terminals.
Claim 10
Dependent Claim 118 words
An integrated circuit, comprising: a plurality of input terminals; a plurality of logic modules each having a plurality of inputs, two or more outputs, and control logic for selectively coupling the inputs to the outputs; a plurality of programmable interconnect circuitry, said interconnect circuitry being adaptable to selectively connect one or more of said logic module for implementing a predefined logic function; and a series of horizontal and vertical track segments, the track segments being selectively connectible by programming antifuses located between each of said adjacent segments; and cross point fuses at the cross points of the horizontal and vertical tracks, said cross point fuses being selectively programmable to connect certain ones of said horizontal and vertical tracks.
Claim 11
Dependent Claim 118 words
An integrated circuit, comprising: a plurality of input terminals; a plurality of logic modules each having a plurality of inputs, two or more outputs, and control logic for selectively coupling the inputs to the outputs; a plurality of programmable interconnect circuitry, said interconnect circuitry being adaptable to selectively connect one or more of said logic module for implementing a predefined logic function; and a series of horizontal and vertical track segments, the track segments being selectively connectible by programming antifuses located between each of said adjacent segments; and cross point fuses at the cross points of the horizontal and vertical tracks, said cross point fuses being selectively programmable to connect certain ones of said horizontal and vertical tracks.
Claim 12
Dependent Claim 29 words
The integrated circuit of claim 9, wherein said plurality of the logic modules are formed in rows interspersed with routing channels consisting of predefined tracks of horizontal interconnection segments.

References Cited (Backward Citations)

US4918440A Cited
US5003200A Cited
US4992680A Cited
US5144166A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-08-15 1998-02-14 1998-08-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-08-15 2002-02-14 2002-08-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-08-15 2006-02-14 2006-08-16 $7700.00 Window Closed / Lapsed

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