Patent US5341092A successfully refreshed from Google Patents.
US5341092A
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Testability architecture and techniques for programmable interconnect architecture
Assignee: Microsemi SoC Corp
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Filing: 1992-10-07
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Granted: 1994-08-23
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Expires: 2012-10-07
Abstract
Abstract In an integrated circuit including a first conductor disposed in a first direction, a plurality of second conductors forming intersections with the first conductor, and a plurality of antifuses connected between the first conductor and the second conductors at the intersections, a method for testing the integrity of the plurality of antifuses after attempting to program a selected one of the antifuses, including the steps of precharging each of the second conductors to a first preselected voltage potential such that a selected dynamic voltage is placed on each of the second conductors; placing a second voltage potential on the first conductor, wherein the difference between the first voltage potential and the second voltage potential is less than the voltage necessary to cause degradation of a good antifuse; waiting a preselected time; and sensing the voltage potential on each of the second conductors.
Inventors
- 👤 Khaled A. El-Ayat
- 👤 Jia-Hwang Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:28
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
142 words
In an integrated circuit including a first conductor disposed in a first direction, a plurality of second conductors forming intersections with said first conductor, and a plurality of antifuses connected between said first conductor and said second conductors at said intersections, a method for testing the integrity of said plurality of antifuses after attempting to program a selected one of said antifuses, including the steps of: precharging each of said second conductors to a first preselected voltage potential such that a selected dynamic voltage is placed on each of said second conductors; placing a second voltage potential on said first conductor, wherein the difference between said first voltage potential and said second voltage potential is less than the voltage necessary to cause degradation of a good antifuse; waiting a preselected time; and sensing the voltage potential on each of said second conductors.
Claim 2
Dependent Claim
142 words
In an integrated circuit including a first conductor disposed in a first direction, a plurality of second conductors forming intersections with said first conductor, and a plurality of antifuses connected between said first conductor and said second conductors at said intersections, a method for testing the integrity of said plurality of antifuses after attempting to program a selected one of said antifuses, including the steps of: precharging each of said second conductors to a first preselected voltage potential such that a selected dynamic voltage is placed on each of said second conductors; placing a second voltage potential on said first conductor, wherein the difference between said first voltage potential and said second voltage potential is less than the voltage necessary to cause degradation of a good antifuse; waiting a preselected time; and sensing the voltage potential on each of said second conductors.
Claim 3
Dependent Claim
69 words
The method of claim 1 wherein the step of sensing the voltage on each of said second conductors comprises the steps of: sensing the voltage on each of said second conductors at a predetermined time after precharging each of said second conductors; storing signals related to the voltages sensed on said second conductors at said predetermined time; and communicating said signals to an input/output pad of said integrated circuit.
Claim 4
Dependent Claim
128 words
In an integrated circuit including a first conductor disposed in a first direction, a plurality of second conductors forming intersections with said first conductor, and a plurality of antifuses connected between said first conductor and said second conductors at said intersections, a method for testing the integrity of said plurality of antifuses after attempting to program a selected one of said antifuses, including the steps of: placing a first preselected voltage potential on each of said second conductors; placing a second voltage potential on said first conductor, wherein the difference between said first voltage potential and said second voltage potential is less than the voltage necessary to cause degradation of a good antifuse; waiting a preselected time; and sensing the voltage potential on each of said second conductors.
Claim 5
Dependent Claim
128 words
In an integrated circuit including a first conductor disposed in a first direction, a plurality of second conductors forming intersections with said first conductor, and a plurality of antifuses connected between said first conductor and said second conductors at said intersections, a method for testing the integrity of said plurality of antifuses after attempting to program a selected one of said antifuses, including the steps of: placing a first preselected voltage potential on each of said second conductors; placing a second voltage potential on said first conductor, wherein the difference between said first voltage potential and said second voltage potential is less than the voltage necessary to cause degradation of a good antifuse; waiting a preselected time; and sensing the voltage potential on each of said second conductors.
Claim 6
Dependent Claim
69 words
The method of claim 3 wherein the step of sensing the voltage on each of said second conductors comprises the steps of: sensing the voltage on each of said second conductors at a predetermined time after precharging each of said second conductors; storing signals related to the voltages sensed on said second conductors at said predetermined time; and communicating said signals to an input/output pad of said integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-22 | 1998-02-21 | 1998-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-22 | 2002-02-21 | 2002-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-22 | 2006-02-21 | 2006-08-23 | $7700.00 | Window Closed / Lapsed |