US4912677A
Expired / Lapsed
US
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Programmable logic device
Assignee: Fujitsu VLSI Ltd
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Filing: 1988-06-10
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Granted: 1990-03-27
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Expires: 2008-06-10
Abstract
Abstract A programmable logic device includes an AND array; an OR array; a buffer circuit connected between the AND array and OR array; and a number of decoder arrangements operatively connected to the AND array and OR array. By constituting the buffer such that the AND array and OR array are electrically associated even in a write operation of data, namely, the buffer is brought to an enable state, a logic verify of the buffer becomes unnecessary and, accordingly, a verify/check of written data can be carried out both easily and efficiently.
Inventors
- 👤 Kiyoshi Itano
- 👤 Kohji Shimbayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:24
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
256 words
A programmable logic device, comprising: an AND array having a programmable memory cell provided at each intersection between a plurality of input term lines and a first plurality of product term lines; an OR array having a programmable memory cell provided at each intersection between a second plurality of product term lines of the same number as said first plurality of product term lines and a plurality of output term lines; a first decoder arrangement operatively connected to said AND array and selecting one of said input term lines in response to a first address signal when said AND array is selected; a second decoder arrangement operatively connected to said AND array and selecting one of said first product term lines in response to a second address signal when one of said AND array and said OR array is selected; a third decoder arrangement operatively connected to said OR array and selecting one of said output term lines in response to a third address signal when said OR array is selected; and a buffer circuit, operatively connected between said first plurality of product term lines and said second plurality of product term lines for converting a first voltage of a first product term line selected by said second decoder arrangement to a second voltage which is higher than said first voltage and applying said converted second voltage to a corresponding second product term line, wherein programming of a programmable memory cell in said OR array selected by said second and third decoder arrangements is carried out.
Claim 2
Dependent Claim
256 words
A programmable logic device, comprising: an AND array having a programmable memory cell provided at each intersection between a plurality of input term lines and a first plurality of product term lines; an OR array having a programmable memory cell provided at each intersection between a second plurality of product term lines of the same number as said first plurality of product term lines and a plurality of output term lines; a first decoder arrangement operatively connected to said AND array and selecting one of said input term lines in response to a first address signal when said AND array is selected; a second decoder arrangement operatively connected to said AND array and selecting one of said first product term lines in response to a second address signal when one of said AND array and said OR array is selected; a third decoder arrangement operatively connected to said OR array and selecting one of said output term lines in response to a third address signal when said OR array is selected; and a buffer circuit, operatively connected between said first plurality of product term lines and said second plurality of product term lines for converting a first voltage of a first product term line selected by said second decoder arrangement to a second voltage which is higher than said first voltage and applying said converted second voltage to a corresponding second product term line, wherein programming of a programmable memory cell in said OR array selected by said second and third decoder arrangements is carried out.
Claim 3
Dependent Claim
87 words
A device as set forth in claim 1, wherein said buffer circuit includes a first transistor connected to a first power supply line changeable between two voltage values and a second transistor connected between said first transistor and a second power supply line which is lower than said first power supply line, and in response to a signal level present at a first product term line, driving a corresponding second product term line, thereby being brought to an enable state even in a write operation of data.
Claim 4
Dependent Claim
65 words
A device as set forth in claim 2, wherein said first transistor and said second transistor constitute an inverter and a third N channel type transistor is connected between an input of said inverter and said first product term line, a gate of said third transistor receiving a bias voltage preset to a half of a voltage employed in a normal operation of said device.
Claim 5
Dependent Claim
60 words
A device as set forth in claim 3, wherein said inverter is composed of an N type metal oxide semiconductor structure and a fourth P channel type transistor is connected between said input of said inverter and a power supply line employed in said normal operation, a gage of said fourth transistor being connected to said second power supply line.
Claim 6
Dependent Claim
55 words
A device as set forth in claim 3, wherein said inverter is composed of a complementary metal oxide semiconductor structure and a fifth P channel type transistor is connected between said input of said inverter and said first power supply line, a gate of said fifth transistor being connected to said second power supply line.
Claim 7
Dependent Claim
55 words
A device as set forth in claim 2, wherein said first power supply line changeable between two voltage values normally has a voltage necessary for a normal operation of said device and is changed to a voltage higher than said voltage necessary for normal device operation when said write operation of data is carried out.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-26 | 1993-09-25 | 1994-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-26 | 1997-09-25 | 1998-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-26 | 2001-09-25 | 2002-03-27 | $7700.00 | Window Closed / Lapsed |