EPROM memory device having a test circuit

Claim 1

An EPROM device having a standard mode and a test mode, comprising: a plurality of reprogrammable memory cells arranged in the form of a matrix; first decoding means adapted to receive a first address signal and connected to row lines of said matrix; second decoding means adapted to receive a second address signal and connected to column lines of said matrix; selection control means connected to either one of said first and second decoding means for controlling such that a predetermined number of two or more of said row or column lines are selected for operation at the same time when said device is in said test mode, said selection control means including at least one test pad to which a test signal is applied, at least a pair of output terminals which are connected to the corresponding one of said first and second decoding means, a first inverter having a first threshold level and connected between said test pad and one of said pair of output terminals, a second inverter having a second threshold level, which is different from said first threshold level, connected between said interconnection and the other of said pair of output terminals, and a MOSFET connected between an interconnection between said test pad and said first inverter and a first reference potential and having its gate connected to a second reference potential which is different from said first reference potential; and write/read means for writing information into or reading information from those memory cells located at the selected row and column lines.