Memory array with redundant elements

Claim 1

In a memory array formed on a semiconductor chip comprising memory cells arranged in rows and columns, some of the columns being "standard" columns and at least one of the columns being initially a "spare" to be substituted for a "standard" column which includes a defective cell, and including a decoder for selectively energizing selected ones of said columns, the improvement comprising: a plurality of programmable non-voltatile electrically alterable elements, each one of said elements having a main conduction path and a control electrode; a first set of said programmable non-voltatile electrically alterable elements having their main conduction paths connected between the "standard" columns and respective decoder outputs for providing a low impendance conduction path between respective decoder outputs and those standard columns having no defective elements and for effectively disconnecting the decoder output from a standard column containing a defective element; and a second set of said programmable non-volatile electrically alterable elements having their main conduction paths connected between the decoder and a spare column for substituting said at least one spare column for said standard column containing a defective element by providing a low impendance path between the spare column and a decoder output effectively disconnected from a standard column containing a defective element.