Field programmable logic array with speed optimized architecture

Claim 2

An integrated circuit, comprising: a) a plurality of circuit input lines; b) a plurality of logical AND gates; c) a first programmable matrix, coupling said plurality of input lines to the inputs of said plurality of logical AND gates; d) a first plurality of logical OR gates, each OR gate having only a single output line, capable of coupling to only a single input of a single device; e) a second programmable matrix, coupling the outputs of said plurality of logical AND gates to the inputs of said first plurality of logical OR gates; f) a second plurality of logical OR gates, each of the second plurality of logical OR gates having only a first and second input, the first input coupled directly to the single output of one of said first plurality of logical OR gates; and g) a third plurality of logical OR gates having only two inputs, each input coupled to a single output from one of said first plurality of logical OR gates, and each of the third plurality of logical OR gates having only one output that is coupled to one of the second inputs from said second plurality of logical OR gates.

Claim 3

An integrated circuit as in claim 1, further comprising: a plurality of output lines coupled to the outputs of said second plurality of logical OR gates.

Claim 4

The integrated circuit as in claim 1, wherein said first and second programmable matrices comprise: an anti-fuse having a dielectric layer for programming particular selectable circuit paths.

Claim 5

A programmable logic device, comprising: a) a plurality of circuit input lines; b) a first set of logic devices providing for logical AND functioning; c) a first matrix array coupling input lines to the inputs of said first set; d) a second set of logic devices providing for logical OR functioning; e) a second matrix array coupling the outputs of said first set to the inputs of said second set; and f) a third set of logic devices providing for logical OR functioning; g) a fourth set of logic devices, providing for logical OR functioning, interposed between said second and third set of logic devices, having exclusively all inputs to said fourth set coupled to the outputs of said first set, and each output from said fourth set is exclusively coupled to a single input of a single logic device in said third set.

Claim 6

A programmable logic device, comprising: a) a plurality of circuit input lines; b) a first set of logic devices providing for logical AND functioning; c) a first matrix array coupling input lines to the inputs of said first set; d) a second set of logic devices providing for logical OR functioning; e) a second matrix array coupling the outputs of said first set to the inputs of said second set; and f) a third set of logic devices providing for logical OR functioning; g) a fourth set of logic devices, providing for logical OR functioning, interposed between said second and third set of logic devices, having exclusively all inputs to said fourth set coupled to the outputs of said first set, and each output from said fourth set is exclusively coupled to a single input of a single logic device in said third set.

Claim 7

A programmable logic device as in claim 4, wherein: said first matrix is programmable.

Claim 8

A programmable logic device as in claim 4, wherein: said second matrix is programmable.

Claim 9

A programmable logic circuit, comprising: a) a first plurality of logical OR gates; b) a plurality of circuit input lines; c) a programmable matrix, coupling said circuit input lines to the inputs of said first plurality of logical OR gates; d) a second plurality of logical OR gates having at least one input coupled to at least one output from said first plurality of logical OR gates, and having at least one other input not directly coupled to said first plurality of logical OR gates; and e) a third plurality of logical OR gates having inputs coupled to the outputs of said first plurality of logical OR gates, and having outputs coupled to at least one other input of said second plurality of logical OR gates.

Claim 10

A programmable logic circuit, comprising: a) a first plurality of logical OR gates; b) a plurality of circuit input lines; c) a programmable matrix, coupling said circuit input lines to the inputs of said first plurality of logical OR gates; d) a second plurality of logical OR gates having at least one input coupled to at least one output from said first plurality of logical OR gates, and having at least one other input not directly coupled to said first plurality of logical OR gates; and e) a third plurality of logical OR gates having inputs coupled to the outputs of said first plurality of logical OR gates, and having outputs coupled to at least one other input of said second plurality of logical OR gates.

Claim 11

A programmable logic circuit as in claim 7, further comprising: a plurality of circuit output lines coupled to the outputs of said second plurality of logical OR gates.

Claim 12

A programmable logic device, comprising: a) a plurality of logical OR gates; b) a plurality of output lines coupled to the outputs of some of said plurality of logical OR gates; c) each of said plurality of output lines having: i) an optimized signal speed path having a first number of logical OR gate delays; and ii) a non-optimized signal speed path having a second number of logical OR gate delays being larger than said first number of logical OR gate delays.

Claim 13

A programmable logic device, comprising: a) a plurality of logical OR gates; b) a plurality of output lines coupled to the outputs of some of said plurality of logical OR gates; c) each of said plurality of output lines having: i) an optimized signal speed path having a first number of logical OR gate delays; and ii) a non-optimized signal speed path having a second number of logical OR gate delays being larger than said first number of logical OR gate delays.

Claim 14

A programmable logic device, comprising: a) a plurality of logical OR gates; b) a plurality of signal paths through said plurality of logical OR gates; and c) said plurality of signal paths comprising: i) a plurality of optimized signal speed paths having a first number of logical OR gate delays; and ii) a plurality of non-optimized signal speed paths having a second number of logical OR gate delays being greater than said first number of logical OR gate delays.

Claim 15

A programmable logic device, comprising: a) a plurality of logical OR gates; b) a plurality of signal paths through said plurality of logical OR gates; and c) said plurality of signal paths comprising: i) a plurality of optimized signal speed paths having a first number of logical OR gate delays; and ii) a plurality of non-optimized signal speed paths having a second number of logical OR gate delays being greater than said first number of logical OR gate delays.

Claim 16

The programmable logic device as in claim 10, wherein, said plurality of non-optimized signal speed paths further comprises: a plurality of equal signal speed paths, where each of said equal signal speed paths have a same number of logical OR gate delays.

Claim 17

The programmable logic device as in claim 10, wherein said plurality of logical OR gates comprises: programmable inputs to said logical OR gates for providing a fully programmable OR matrix.

Claim 18

A programmable logic device, comprising: a) a programmable AND matrix having: inputs to a programmable matrix array, and groups of AND gates receiving inputs from the programmable matrix; and b) a first plurality of OR gates (38) having: groups of OR gates therein, where the first group of OR gates has at least one input associated with the first group of AND gates; at least another second input not directly coupled to a group of AND gates; c) a second plurality of OR gates, having: groups of OR gates therein, where the first group of OR gates has no inputs from the first group of AND gates; and the output of at least one of said first group of OR gates being coupled to the another second input to said first group of OR gates.

Claim 19

A programmable logic device, comprising: a) a programmable AND matrix having: inputs to a programmable matrix array, and groups of AND gates receiving inputs from the programmable matrix; and b) a first plurality of OR gates (38) having: groups of OR gates therein, where the first group of OR gates has at least one input associated with the first group of AND gates; at least another second input not directly coupled to a group of AND gates; c) a second plurality of OR gates, having: groups of OR gates therein, where the first group of OR gates has no inputs from the first group of AND gates; and the output of at least one of said first group of OR gates being coupled to the another second input to said first group of OR gates.

Claim 20

A programmable logic device, comprising: a) a plurality of AND gates divided into first, second, and third groups; b) a primary plurality of OR gates divided into first primary, second primary, and third primary groups, having: the first primary group exclusively electrically associated with the first group of AND gates; the second primary group exclusively electrically associated with the second group of AND gates; the third primary group exclusively electrically associated with the third group of AND gates; c) a secondary plurality of OR gates divided into first secondary (38A), second secondary, and third secondary groups, having: the first second group having an input exclusively and directly coupled to one of the OR gates from the first primary group, and another input not electrically associated with the first primary group; the second secondary group having an input exclusively and directly coupled to one of the OR gates from the second primary group, and another input not electrically associated with the second primary group; and the third secondary group having an input exclusively and directly coupled to one of the OR gates from the third primary group, and another input not electrically associated with the third primary group; and d) an intermediate array of OR gates, divided into first intermediate, second intermediate, and third intermediate groups, having: all inputs of the intermediate array electrically associated with the first OR array, and all outputs of the intermediate array electrically associated with the secondary OR array inputs; the first intermediate group having no inputs electrically associated to the first primary group of OR gates, and having outputs exclusively electrically associated with the first secondary group of OR gates; the second intermediate group having no inputs electrically associated to the second primary group of OR gates, and having outputs exclusively electrically associated with the second secondary group of OR gates; and the third intermediate group having no inputs electrically associated to the third primary group of OR gates, and having outputs exclusively electrically associated with the third secondary group of OR gates.

Claim 21

A programmable logic device, comprising: a) a plurality of AND gates divided into first, second, and third groups; b) a primary plurality of OR gates divided into first primary, second primary, and third primary groups, having: the first primary group exclusively electrically associated with the first group of AND gates; the second primary group exclusively electrically associated with the second group of AND gates; the third primary group exclusively electrically associated with the third group of AND gates; c) a secondary plurality of OR gates divided into first secondary (38A), second secondary, and third secondary groups, having: the first second group having an input exclusively and directly coupled to one of the OR gates from the first primary group, and another input not electrically associated with the first primary group; the second secondary group having an input exclusively and directly coupled to one of the OR gates from the second primary group, and another input not electrically associated with the second primary group; and the third secondary group having an input exclusively and directly coupled to one of the OR gates from the third primary group, and another input not electrically associated with the third primary group; and d) an intermediate array of OR gates, divided into first intermediate, second intermediate, and third intermediate groups, having: all inputs of the intermediate array electrically associated with the first OR array, and all outputs of the intermediate array electrically associated with the secondary OR array inputs; the first intermediate group having no inputs electrically associated to the first primary group of OR gates, and having outputs exclusively electrically associated with the first secondary group of OR gates; the second intermediate group having no inputs electrically associated to the second primary group of OR gates, and having outputs exclusively electrically associated with the second secondary group of OR gates; and the third intermediate group having no inputs electrically associated to the third primary group of OR gates, and having outputs exclusively electrically associated with the third secondary group of OR gates.

Claim 22

The programmable logic device of claim 14, further comprising: a fourth array of OR gates positioned to receive inputs from the intermediate OR array and to electrically couple the outputs of the fourth array to the secondary OR array inputs.

Claim 23

A PLD having inputs, comprising: a) AND logic means for performing AND logic on the PLD inputs; b) first OR logic means, coupled to the AND logic means outputs, for performing OR logic on the outputs from the AND logic means, and having outputs; c) second OR logic means, coupled exclusively to outputs from said first OR logic means, for performing OR logic on the first OR logic means outputs; and d) third OR logic means, coupled exclusively to receive resulting electrical outputs from both said first and said second OR logic means.

Claim 24

A PLD having inputs, comprising: a) AND logic means for performing AND logic on the PLD inputs; b) first OR logic means, coupled to the AND logic means outputs, for performing OR logic on the outputs from the AND logic means, and having outputs; c) second OR logic means, coupled exclusively to outputs from said first OR logic means, for performing OR logic on the first OR logic means outputs; and d) third OR logic means, coupled exclusively to receive resulting electrical outputs from both said first and said second OR logic means.

Claim 25

The PLD of claim 16, wherein said first OR logic means is a set of OR logic gates.

Claim 26

The PLD of claim 17, wherein said second OR logic means is a set of OR logic gates.

Claim 27

The PLD of claim 18, wherein said AND logic means is a set of AND logic gates.

Claim 28

A PLD with inputs, comprising: a) AND array means, for performing logical AND functions on the PLD inputs; b) first OR array means, coupled to the outputs of the AND array means, for performing OR functions on the outputs from the AND array; c) second OR array means, coupled to the outputs of the first OR array exclusively; d) third OR array means, coupled to both the first and second OR array outputs; and e) optimized path means, coupled to the first OR array, for routing selected optimized signals directly from the PLD inputs to the AND array means, to the first OR array means, directly to the third OR array means, and to the PLD outputs.

Claim 29

A PLD with inputs, comprising: a) AND array means, for performing logical AND functions on the PLD inputs; b) first OR array means, coupled to the outputs of the AND array means, for performing OR functions on the outputs from the AND array; c) second OR array means, coupled to the outputs of the first OR array exclusively; d) third OR array means, coupled to both the first and second OR array outputs; and e) optimized path means, coupled to the first OR array, for routing selected optimized signals directly from the PLD inputs to the AND array means, to the first OR array means, directly to the third OR array means, and to the PLD outputs.