Electrically-erasable, electrically-programmable read-only memory cell, an array of such cells and methods for making and using the same

Claim 1

A method for using an electrically-erasable, electrically-programmable read-only memory cell formed at a face of a layer of semiconductor of a first conductivity type and including first and second source/drain regions formed in the face of a second conductivity type opposite the first conductivity type and spaced by a first channel area, a third source/drain region formed in the face of the second conductivity type and spaced from the second source/drain region by a second channel area, a thick insulator region formed adjacent at least a portion of the second source/drain region remote from the first channel and having a lateral margin of sloped thickness overlying a corresponding lateral margin of the second source/drain region, the corresponding lateral margin of the second source/drain region having a graded dopant concentration directly proportionate with the sloped thickness of the overlying lateral margin of the thick insulator, a differentially grown insulator region overlying the second source/drain and having a lateral margin of sloped thickness, a thin insulator tunneling window overlying an area of the second source/drain region, the tunneling window formed between and spacing the lateral margin of the thick insulator region and the lateral margin of the differentially grown insulator region, a floating gate conductor disposed adjacent the tunneling window and insulatively adjacent the first channel area a gate conductor insulatively adjacent the second channel area, and a control gate conductor insulatively adjacent the floating gate conductor, the method comprising the steps of: programming the memory cell, said step of programming the memory cell comprising the substeps of: applying a high voltage to the gate conductor; applying a high voltage to the control gate conductor; applying approximately zero volts to the first source/drain region; allowing the second source/drain region to float; and in response to said substeps of applying voltages charging the floating gate conductor with electrons via Fowler-Nordheim tunneling; reading the memory cell, said step of reading comprising the substeps of: applying a select voltage to the gate conductor; applying a sense voltage to the control gate conductor; applying a reading voltage to the first source/drain region; applying approximately zero volts to the second source/drain region; and in response to said substeps of applying voltages, measuring current flow between the first source/drain region and the second source/drain region thereby reading the cell; and erasing the memory cell, said step of erasing comprising the substeps of: applying a high voltage to the gate conductor; applying approximately zero volts to the control gate conductor; applying a high voltage to the first source/drain region; allowing the second source/drain region to float; and in response to said steps of applying voltages, removing electrons from the floating gate conductor via Fowler-Nordheim tunneling.

Claim 2

A method for using an electrically-erasable, electrically-programmable read-only memory cell formed at a face of a layer of semiconductor of a first conductivity type and including first and second source/drain regions formed in the face of a second conductivity type opposite the first conductivity type and spaced by a first channel area, a third source/drain region formed in the face of the second conductivity type and spaced from the second source/drain region by a second channel area, a thick insulator region formed adjacent at least a portion of the second source/drain region remote from the first channel and having a lateral margin of sloped thickness overlying a corresponding lateral margin of the second source/drain region, the corresponding lateral margin of the second source/drain region having a graded dopant concentration directly proportionate with the sloped thickness of the overlying lateral margin of the thick insulator, a differentially grown insulator region overlying the second source/drain and having a lateral margin of sloped thickness, a thin insulator tunneling window overlying an area of the second source/drain region, the tunneling window formed between and spacing the lateral margin of the thick insulator region and the lateral margin of the differentially grown insulator region, a floating gate conductor disposed adjacent the tunneling window and insulatively adjacent the first channel area a gate conductor insulatively adjacent the second channel area, and a control gate conductor insulatively adjacent the floating gate conductor, the method comprising the steps of: programming the memory cell, said step of programming the memory cell comprising the substeps of: applying a high voltage to the gate conductor; applying a high voltage to the control gate conductor; applying approximately zero volts to the first source/drain region; allowing the second source/drain region to float; and in response to said substeps of applying voltages charging the floating gate conductor with electrons via Fowler-Nordheim tunneling; reading the memory cell, said step of reading comprising the substeps of: applying a select voltage to the gate conductor; applying a sense voltage to the control gate conductor; applying a reading voltage to the first source/drain region; applying approximately zero volts to the second source/drain region; and in response to said substeps of applying voltages, measuring current flow between the first source/drain region and the second source/drain region thereby reading the cell; and erasing the memory cell, said step of erasing comprising the substeps of: applying a high voltage to the gate conductor; applying approximately zero volts to the control gate conductor; applying a high voltage to the first source/drain region; allowing the second source/drain region to float; and in response to said steps of applying voltages, removing electrons from the floating gate conductor via Fowler-Nordheim tunneling.