Electrically programmable and erasable memory cells with field plate conductor defined drain regions

Claim 2

First and second electrically erasable and programmable memory cells formed at a face of a semiconductor layer of a first conductivity type, comprising: first and second source regions formed in said layer at said face to be of a second conductivity type opposite said first conductivity type and to be spaced apart; a field plate conductor insulatively disposed adjacent said face and laterally spaced from and between said first and second source regions; an inversion region disposed in said layer adjacent said field plate conductor and inverted from said first conductivity type to said second conductivity type upon application of a predetermined voltage to said field plate conductor; a first channel region defined in said layer between said first source region and said inversion region, a second channel region defined in said layer between said second source region and said inversion region, each channel region comprising floating gate and control gate subchannel regions; a drain contact region adjoining region for selective connection to a drain read voltage source; first and second floating gate conductors insulatively disposed adjacent respective ones of said first and second source regions so as to be capable of being programmed thereby, each said floating gate conductor further insulatively disposed adjacent a respective floating gate subchannel region to control the conductance thereof; and a control gate conductor insulatively disposed adjacent said control gate subchannel regions to control the conductance thereof and further insulatively disposed adjacent said floating gate conductors for the programming and erasure of said floating gate conductors.

Claim 3

The cells of claim 1, and further comprising: thick insulator regions formed at said face over said first and second source regions; for each said source region, a thin window insulator layer formed at said face adjacent one side of said thick insulator layer, said one side separated from a respective channel region by said thick insulator layer; and for each said source region, a respective floating gate conductor formed on said window insulator layer so as to permit programming thereof through Fowler-Nordheim tunneling.

Claim 4

The cells of claim 2, wherein a respective thick isolating insulator layer is formed at said face near said one side of each source region; said thin window insulator layer formed between said thick isolating insulator layer and said thick insulator layer formed over a respective source region.

Claim 5

The cells of claim 1, wherein said drain contact region is remote from said channel regions.

Claim 6

A nonvolatile memory cell formed at a face of a semiconductor layer of a first conductivity type, comprising: a source region formed in said layer to be of a second conductivity type opposite said first conductivity type; a field plate conductor insulatively disposed adjacent said face and spaced from said source region, an inversion region in said layer defined by said field plate conductor and inverted from said first conductivity type to said second conductivity type in response to a predetermined voltage applied to said field plate conductor; a drain contact region adjoining said inversion region for selective connection to a drain read voltage source; a channel region defined in said layer between said source region and said inversion region and comprising floating gate and control gate subregions; a floating gate conductor insulatively disposed adjacent said source region so as to be capable of being selectively programmed thereby, said floating gate conductor further insulatively disposed adjacent said floating gate subregion to control the conductance thereof; and a control gate conductor insulatively disposed adjacent said control gate subregion to control the conductance thereof and further insulatively disposed adjacent said floating gate conductor for the programming and erasure of said floating gate conductor.

Claim 7

A nonvolatile memory cell formed at a face of a semiconductor layer of a first conductivity type, comprising: a source region formed in said layer to be of a second conductivity type opposite said first conductivity type; a field plate conductor insulatively disposed adjacent said face and spaced from said source region, an inversion region in said layer defined by said field plate conductor and inverted from said first conductivity type to said second conductivity type in response to a predetermined voltage applied to said field plate conductor; a drain contact region adjoining said inversion region for selective connection to a drain read voltage source; a channel region defined in said layer between said source region and said inversion region and comprising floating gate and control gate subregions; a floating gate conductor insulatively disposed adjacent said source region so as to be capable of being selectively programmed thereby, said floating gate conductor further insulatively disposed adjacent said floating gate subregion to control the conductance thereof; and a control gate conductor insulatively disposed adjacent said control gate subregion to control the conductance thereof and further insulatively disposed adjacent said floating gate conductor for the programming and erasure of said floating gate conductor.

Claim 8

The cell of claim 5, wherein said drain contact region is remote from said channel region.

Claim 9

A nonvolatile memory cell formed at a face of a semiconductor layer of a first conductivity type, comprising: a source region formed in said layer at said face to be of a second conductivity type opposite said first conductivity type; a drain region formed in said layer at said face to be of said second conductivity type, a channel region of said layer spacing said source region from said drain region and comprising first, second and third subchannel regions; a floating gate conductor insulatively disposed adjacent said source region so as to be capable of being selectively programmed thereby, and insulatively disposed adjacent said first subchannel region to control the conductance thereof; a field plate conductor insulatively disposed adjacent said second subchannel regions to control the conductance thereof; and a control gate conductor insulatively disposed adjacent said third subchannel region to control the conductance thereof and further insulatively disposed adjacent said floating gate conductor for the programming and erasure of said floating gate conductor.

Claim 10

A nonvolatile memory cell formed at a face of a semiconductor layer of a first conductivity type, comprising: a source region formed in said layer at said face to be of a second conductivity type opposite said first conductivity type; a drain region formed in said layer at said face to be of said second conductivity type, a channel region of said layer spacing said source region from said drain region and comprising first, second and third subchannel regions; a floating gate conductor insulatively disposed adjacent said source region so as to be capable of being selectively programmed thereby, and insulatively disposed adjacent said first subchannel region to control the conductance thereof; a field plate conductor insulatively disposed adjacent said second subchannel regions to control the conductance thereof; and a control gate conductor insulatively disposed adjacent said third subchannel region to control the conductance thereof and further insulatively disposed adjacent said floating gate conductor for the programming and erasure of said floating gate conductor.

Claim 11

The memory cell of claim 7, wherein said filed plate conductor is disposed laterally adjacent said drain region.

Claim 12

First and second nonvolatile memory cells formed at a face of a semiconductor layer of a first conductivity type, comprising: first and second source regions formed in said layer at said face to be of a second conductivity type opposite said first conductivity type and to be spaced apart; a drain region formed in said layer at said face to be of said second conductivity type and formed between said first and second source regions, a first channel region defined in said layer between said first source region and said drain region, a second channel region defining said layer between said second source region and said inversion region, each channel region comprising first and second subchannel regions, at least one of said channel regions further including a third subchannel region, each of said subchannel regions in any one channel region required to be conductive for the last said channel region to be conductive; first and second floating gate conductors insulatively disposed adjacent respective ones of said first and second source regions so as to be capable of being programmed thereby, each said floating gate conductors further insulatively disposed adjacent a respective first subchannel region to control the conductance thereof; a control gate conductor insulatively disposed adjacent said second subchannel regions to control the conductance thereof and further insulatively disposed adjacent said floating gate conductors for the programming and erasure of said conductors; and for each third subchannel region, a field plate conductor insulatively disposed adjacent thereto to control the conductance thereof.

Claim 13

First and second nonvolatile memory cells formed at a face of a semiconductor layer of a first conductivity type, comprising: first and second source regions formed in said layer at said face to be of a second conductivity type opposite said first conductivity type and to be spaced apart; a drain region formed in said layer at said face to be of said second conductivity type and formed between said first and second source regions, a first channel region defined in said layer between said first source region and said drain region, a second channel region defining said layer between said second source region and said inversion region, each channel region comprising first and second subchannel regions, at least one of said channel regions further including a third subchannel region, each of said subchannel regions in any one channel region required to be conductive for the last said channel region to be conductive; first and second floating gate conductors insulatively disposed adjacent respective ones of said first and second source regions so as to be capable of being programmed thereby, each said floating gate conductors further insulatively disposed adjacent a respective first subchannel region to control the conductance thereof; a control gate conductor insulatively disposed adjacent said second subchannel regions to control the conductance thereof and further insulatively disposed adjacent said floating gate conductors for the programming and erasure of said conductors; and for each third subchannel region, a field plate conductor insulatively disposed adjacent thereto to control the conductance thereof.

Claim 14

The cells of claim 9, wherein each of said channel regions has a third subchannel region whose conductance is controlled by a respective field plate conductor.

Claim 15

The cells of claim 9, wherein only one of said channel regions has said third subchannel region.

Claim 16

An array of electrically erasable and programmable memory cells formed at a face of a semiconductor layer of a first conductivity tYpe, said cells formed in columns and in rows formed at an angle to said columns, the array comprising: a plurality of source regions formed to be elongate in a column direction and formed at said face be of a second conductivity type opposite said first conductivity type, said source regions spaced apart and substantially parallel to each other; for each pair of source regions, an elongate field plate conductor insulatively disposed adjacent said face and laterally spaced from and between said pair of source regions, an inversion region disposed in said layer and laterally defined by said field plate conductor and inverted from said first conductivity type to said second conductivity type upon application of a predetermined voltage to said field plate conductor; for each intersection of a row and a pair of source regions, a first channel region defined in said layer between a first of said pair of source regions and said inversion region, a second channel region defined in said layer between a second of said pair of source regions and said inversion region, each channel region comprising floating gate and control gate subchannel regions; for each floating gate subchannel region, a floating gate conductor insulatively disposed adjacent thereto to control the conductance thereof, each floating gate conductor further insulatively disposed adjacent one of said pair of source regions so as to be capable of being programmed thereby; and for each row, a control gate conductor insulatively disposed adjacent said control gate subchannel regions in said row to control the conductance thereof, and further insulatively disposed adjacent each floating gate conductor in said row for the programming and erasure of said floating gate conductors.

Claim 17

An array of electrically erasable and programmable memory cells formed at a face of a semiconductor layer of a first conductivity tYpe, said cells formed in columns and in rows formed at an angle to said columns, the array comprising: a plurality of source regions formed to be elongate in a column direction and formed at said face be of a second conductivity type opposite said first conductivity type, said source regions spaced apart and substantially parallel to each other; for each pair of source regions, an elongate field plate conductor insulatively disposed adjacent said face and laterally spaced from and between said pair of source regions, an inversion region disposed in said layer and laterally defined by said field plate conductor and inverted from said first conductivity type to said second conductivity type upon application of a predetermined voltage to said field plate conductor; for each intersection of a row and a pair of source regions, a first channel region defined in said layer between a first of said pair of source regions and said inversion region, a second channel region defined in said layer between a second of said pair of source regions and said inversion region, each channel region comprising floating gate and control gate subchannel regions; for each floating gate subchannel region, a floating gate conductor insulatively disposed adjacent thereto to control the conductance thereof, each floating gate conductor further insulatively disposed adjacent one of said pair of source regions so as to be capable of being programmed thereby; and for each row, a control gate conductor insulatively disposed adjacent said control gate subchannel regions in said row to control the conductance thereof, and further insulatively disposed adjacent each floating gate conductor in said row for the programming and erasure of said floating gate conductors.

Claim 18

The array of claim 12, and further comprising: a diffused contact region formed at said face to be of a second conductivity type opposite said first conductivity type and formed in between and spaced from adjacent rows, said contact region adjoining at least one inversion region; a contact area defined within said diffused contact region and insulatively spaced from any field plate conductor; and a conductor formed over said array, a contact formed within said contact area from said diffused contact region to said conductor.

Claim 19

An array of nonvolatile memory cells formed at a face of a semiconductor layer of a first conductivity type, said cells formed in columns and in rows formed at an angle to said columns, said array comprising: a plurality of substantially parallel spaced apart source regions formed in said layer to be elongate in a column direction and to be of a second conductivity type opposite said first conductivity type; for each pair of source regions, a drain region formed in said layer to be elongate in said column direction, said drain region formed between said pair of source regions and to be of said second conductivity type; said pair of source regions and said drain region intersecting a plurality of rows; at each intersection, a first channel region of said layer spacing a first of said pair of source regions from said drain region, a second channel region of said layer spacing a second of said pair of source regions from said drain region, each channel region comprising first and second subchannel regions, at least one of said first and second channel regions further including a third subchannel region; for each of said first subchannel regions, a floating gate conductor insulatively disposed adjacent thereto to control the conductance thereof, each floating gate conductor further insulatively disposed adjacent a source region so as to be capable of being selectively programmed thereby; for each pair of source regions, at least one field plate conductor formed to be elongate in a column direction and to be insulatively disposed adjacent said third subchannel regions in a respective column to control the conductance thereof; and for each row, a control gate conductor insulatively disposed adjacent said second subchannel regions in said row to control the conductance thereof and further insulatively disposed adjacent each said floating gate conductor in said row for the programming and erasure thereof.

Claim 20

An array of nonvolatile memory cells formed at a face of a semiconductor layer of a first conductivity type, said cells formed in columns and in rows formed at an angle to said columns, said array comprising: a plurality of substantially parallel spaced apart source regions formed in said layer to be elongate in a column direction and to be of a second conductivity type opposite said first conductivity type; for each pair of source regions, a drain region formed in said layer to be elongate in said column direction, said drain region formed between said pair of source regions and to be of said second conductivity type; said pair of source regions and said drain region intersecting a plurality of rows; at each intersection, a first channel region of said layer spacing a first of said pair of source regions from said drain region, a second channel region of said layer spacing a second of said pair of source regions from said drain region, each channel region comprising first and second subchannel regions, at least one of said first and second channel regions further including a third subchannel region; for each of said first subchannel regions, a floating gate conductor insulatively disposed adjacent thereto to control the conductance thereof, each floating gate conductor further insulatively disposed adjacent a source region so as to be capable of being selectively programmed thereby; for each pair of source regions, at least one field plate conductor formed to be elongate in a column direction and to be insulatively disposed adjacent said third subchannel regions in a respective column to control the conductance thereof; and for each row, a control gate conductor insulatively disposed adjacent said second subchannel regions in said row to control the conductance thereof and further insulatively disposed adjacent each said floating gate conductor in said row for the programming and erasure thereof.

Claim 23

The method of claim 15, and further comprising the steps of: placing a third predetermined read voltage on the source region; and determining whether a "one" or a "zero" bit resides on the floating gate conductor by sensing the presence or absence of current at the inversion region contact.

Claim 24

The method of claim 15, and further comprising the steps of: placing a third predetermined read voltage on the inversion region contact; and determining the logic state of the floating gate conductor of the cell by sensing the presence or absence of current at the source region.