Patent US4877976A successfully refreshed from Google Patents.
US4877976A
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US
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Cascade FET logic circuits
Assignee: Eneos Corp
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Filing: 1988-10-13
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Granted: 1989-10-31
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Expires: 2008-10-13
Abstract
Abstract A group III-V digital logic circuit which includes either at least two enhancement type metal semiconductor field effect transistors and one load element or two first type field effect transistors having a first threshold voltage and two second type field effect transistors having a second threshold voltage, for providing a logic operation. The second threshold voltage is less than zero and is less than the first threshold voltage. The group III-V digital logic circuit can be formed as an integrated circuit on, in particular, a GaAs substrate. The field effect transistor can be either a metal semiconductor field effect transistor or a junction field effect transistor.
Inventors
- 👤 Lawrence E. Lach
- 👤 Mikiharu Ohoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0952; H03K19/09403
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
213 words
An integrated logic circuit, comprising: a group III-V compound semiconductor substrate; an input signal terminal; an output signal terminal; a first power supply node; a second power supply node; a first field effect transistor on said semiconductor substrate, having a first gate coupled to the input signal terminal, having a first drain coupled to the first power supply node, and having a first source; a second field effect transistor on said semiconductor substrate, having a second gate coupled to said first source of said first field effect transistor, having a second source coupled to the second power supply node, and having a second drain coupled to the output signal terminal; a third field effect transistor of a depletion type, having a third gate, having a third source coupled to the third gate and having a third drain, wherein said first power supply node corresponds to the third drain of said third field effect transistor and the third source of the third field effect transistor is coupled to the output signal terminal; and a fourth field effect transistor having a fourth drain coupled to said first source of said first field effect transistor, having a fourth gate and having a fourth source coupled to said fourth gate and to the second power supply node.
Claim 2
Dependent Claim
213 words
An integrated logic circuit, comprising: a group III-V compound semiconductor substrate; an input signal terminal; an output signal terminal; a first power supply node; a second power supply node; a first field effect transistor on said semiconductor substrate, having a first gate coupled to the input signal terminal, having a first drain coupled to the first power supply node, and having a first source; a second field effect transistor on said semiconductor substrate, having a second gate coupled to said first source of said first field effect transistor, having a second source coupled to the second power supply node, and having a second drain coupled to the output signal terminal; a third field effect transistor of a depletion type, having a third gate, having a third source coupled to the third gate and having a third drain, wherein said first power supply node corresponds to the third drain of said third field effect transistor and the third source of the third field effect transistor is coupled to the output signal terminal; and a fourth field effect transistor having a fourth drain coupled to said first source of said first field effect transistor, having a fourth gate and having a fourth source coupled to said fourth gate and to the second power supply node.
Claim 3
Dependent Claim
15 words
An integrated logic circuit as set forth in claim 1, wherein said substrate is GaAs.
Claim 4
Dependent Claim
23 words
An integrated logic circuit as set forth in claim 1, wherein said fourth field effect transistor is a metal semiconductor field effect transistor.
Claim 5
Dependent Claim
21 words
An integrated logic circuit as set forth in claim 1, wherein said fourth field effect transistor is a junction-field effect transistor.
Claim 6
Dependent Claim
26 words
An integrated logic circuit as set forth in claim 1, wherein said logic circuit operates over a temperature range of at least -50° to 200° C.
Claim 7
Dependent Claim
199 words
An integrated logic circuit coupled to first and second power sources and having input and output signal terminals, comprising: a group III-V compound semiconductor substrate; a first field effect transistor on said substrate, having a first threshold voltage, having a gate coupled to the input signal terminal, having a drain coupled to the first power source, and having a source; a second field effect transistor on said substrate, having a second threshold voltage, having a drain coupled to said source of said first transistor forming a first connection node therebetween, having a gate, and having a source coupled to said gate and to the second power source; a third field effect transistor on said substrate, having the first threshold voltage, having a gate coupled to the first connection node, having a source coupled to the second power source, and having a drain; and a fourth field effect transistor on said substrate, having the second threshold voltage, having a drain coupled to the first power source, having a gate, and having a source coupled to said gate and to said drain of said third transistor, forming a second connection node therebetween, the output terminal coupled to the second connection node.
Claim 8
Dependent Claim
199 words
An integrated logic circuit coupled to first and second power sources and having input and output signal terminals, comprising: a group III-V compound semiconductor substrate; a first field effect transistor on said substrate, having a first threshold voltage, having a gate coupled to the input signal terminal, having a drain coupled to the first power source, and having a source; a second field effect transistor on said substrate, having a second threshold voltage, having a drain coupled to said source of said first transistor forming a first connection node therebetween, having a gate, and having a source coupled to said gate and to the second power source; a third field effect transistor on said substrate, having the first threshold voltage, having a gate coupled to the first connection node, having a source coupled to the second power source, and having a drain; and a fourth field effect transistor on said substrate, having the second threshold voltage, having a drain coupled to the first power source, having a gate, and having a source coupled to said gate and to said drain of said third transistor, forming a second connection node therebetween, the output terminal coupled to the second connection node.
Claim 9
Dependent Claim
24 words
An integrated logic circuit as set forth in claim 6, wherein said first and third field effect transistors are metal semiconductor field effect transistors.
Claim 10
Dependent Claim
23 words
An integrated logic circuit as set forth in claim 6, wherein said first and third field effect transistors are junction field effect transistors.
Claim 11
Dependent Claim
22 words
An integrated logic circuit as set forth in claim 6, wherein said second and fourth field effect transistors are depletion mode transistors.
Claim 12
Dependent Claim
24 words
An integrated logic circuit as set forth in claim 9, wherein said second and fourth field effect transistors are metal semiconductor field effect transistors.
Claim 13
Dependent Claim
23 words
An integrated logic circuit as set forth in claim 9, wherein said second and fourth field effect transistors are junction field effect transistors.
Claim 14
Dependent Claim
70 words
An integrated logic circuit as set forth in claim 6, further comprising: a second input signal terminal; and a fifth field effect transistor on said substrate, having the first threshold voltage, having a gate coupled to the second input signal terminal, having a drain coupled to said drain of said first transistor and to the first power source, and having a source coupled to said source of said first transistor.
Claim 15
Dependent Claim
21 words
An integrated logic circuit as set forth in claim 12, wherein said fifth transistor is a metal semiconductor field effect transistor.
Claim 16
Dependent Claim
20 words
An integrated logic circuit as set forth in claim 12, wherein said fifth transistor is a junction field effect transistor.
Claim 17
Dependent Claim
14 words
An integrated circuit as set forth in claim 12, wherein said substrate is GaAs.
Claim 18
Dependent Claim
19 words
An integrated logic circuit as set forth in claim 12, wherein said logic circuit is a two-input NOR circuit.
Claim 19
Dependent Claim
27 words
An integrated logic circuit as set forth in claim 16, wherein a plurality of said two-input NOR circuits are connected together to form said integrated logic circuits.
Claim 20
Dependent Claim
19 words
An integrated logic circuit as set forth in claim 12, wherein the second threshold voltage is less than zero.
Claim 21
Dependent Claim
30 words
An integrated logic circuit as set forth above with respect to claim 18, wherein said first, second, fourth and third transistors have widths having a ratio of approximately 2-2-2-5, respectively.
Claim 22
Dependent Claim
37 words
An integrated logic circuit as set forth in claim 19, wherein the width each of said first, second and fourth transistors is substantially two micrometers, and wherein the width of said third transistor is substantially five micrometers.
Claim 23
Dependent Claim
22 words
An integrated logic circuit as set forth in claim 19, wherein the first threshold voltage is greater than the second threshold voltage.
Claim 24
Dependent Claim
42 words
An integrated logic circuit as set forth in claim 21, wherein the difference between the first threshold voltage and the second threshold voltage is equal to a constant, said constant being determined in accordance with the widths of said field effect transistors.
Claim 25
Dependent Claim
27 words
An integrated logic circuit as set forth in claim 6, wherein the first and second power sources of said field effect transistors are compatible with silicon circuits.
Claim 26
Dependent Claim
22 words
An integrated logic circuit as set forth in claim 6, wherein said logic circuit includes only the first and second power sources.
Claim 27
Dependent Claim
123 words
A logic circuit, comprising: a first potential node; a second potential node; a first group III-V field effect transistor having a first gate, having a first source, and having a first drain, said first gate receiving an input signal; a second group III-V field effect transistor having a second gate, having a second source, and having a second drain, said first drain and said second drain being coupled at said first node to receive said first potential, said second gate and said second source being coupled together; and a third group III-V field effect transistor having a third source receiving said second potential, having a third drain coupled to said second source, and having a third gate coupled solely to said first source.
Claim 28
Dependent Claim
123 words
A logic circuit, comprising: a first potential node; a second potential node; a first group III-V field effect transistor having a first gate, having a first source, and having a first drain, said first gate receiving an input signal; a second group III-V field effect transistor having a second gate, having a second source, and having a second drain, said first drain and said second drain being coupled at said first node to receive said first potential, said second gate and said second source being coupled together; and a third group III-V field effect transistor having a third source receiving said second potential, having a third drain coupled to said second source, and having a third gate coupled solely to said first source.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-30 | 1993-05-01 | 1993-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-30 | 1997-05-01 | 1997-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-30 | 2001-05-01 | 2001-10-31 | $7700.00 | Window Closed / Lapsed |