Schottky diode-diode field effect transistor logic

Claim 2

A logic circuit, comprising: a plurality of AND logic elements, each AND element including a plurality of Schottky diodes each having an anode and a cathode, with each cathode connected to a logic input and the anodes connected in common to establish an AND output; a diode pull up connected to each AND output and to a source of positive bias potential to raise the level of said AND output; an OR logic element, including a plurality of Schottky diodes each having an anode and a cathode, with each anode connected to one of said AND outputs and the cathodes connected in common to establish an OR output; a first level shifting element connected to said OR output; a diode pull down connected to said OR output and to a source of negative bias potential to lower the level of said OR output; and an output field effect transistor having a source, a gate, and a drain, with the gate connected to said first level shifting element, the source connected to ground, and the drain providing a logic output from said circuit.

Claim 3

The circuit of claim 1, wherein said first level shifting element further comprises a level shifting diode.

Claim 4

The circuit of claim 2, wherein said Schottky diodes and said level shifting diode further comprise GaAs diodes.

Claim 5

The circuit of claim 1, further comprising an output pull up connected to said logic output and said source of positive bias potential to raise the level of said logic output.

Claim 6

The circuit of claim 4, wherein: said output pull up further comprises an output pull up field effect transistor having a source, a gate, and a drain, with the source connected to the drain of said output field effect transistor, the gate connected to the source, and the drain connected to said source of positive bias potential; each of said diode pull ups further comprises a diode pull up field effect transistor having a source, a gate, and a drain, with the source connected to said AND output, the gate connected to the source, and the drain connected to said source of positive bias potential; and said diode pull down further comprises a diode pull down field effect transistor having a source, a gate, and a drain, with the source connected to said source of negative bias potential, the gate connected to the source, and the drain connected to the gate of said output field effect-transistor.

Claim 7

The circuit of claim 5, wherein said output pull up, said diode pull ups, and said diode down each further comprises a depletion mode GaAs field effect transistor.

Claim 8

The circuit of claim 6, wherein said output pull up, said diode pull ups, and said diode pull down each further comprises a depletion mode GaAs Schottky barrier field effect transistor.

Claim 9

The circuit of claim 1, further comprising a driver stage, including: a source follower driver connected between said source of positive bias potential and the gate of said output field effect transistor for receiving said OR output; and a source follower pull down connected between the gate of said output field effect transistor and said source of negative bias potential.

Claim 10

The circuit of claim 8, wherein: said source follower driver further comprises a source follower driver field effect transistor having a source, a gate, and a drain, with the source connected to the gate of said output field effect transistor, the gate connected to said OR output, and the drain connected to said source of positive bias potential; and said source follower pull down further comprises a source follower pull down field effect transistor having a source, a gate, and a drain, with the source connected to said source of negative bias potential, the gate connected to the source, and the drain connected to the gate of said output field effect transistor.

Claim 11

The circuit of claim 9, wherein said source follower driver and said source follower pull down each further comprises a depletion mode GaAs field effect transistor.

Claim 12

The circuit of claim 10, wherein said source follower driver and said source follower pull down each further comprises a depletion mode GaAs Schottky barrier field effect transistor.

Claim 13

The circuit of claim 9, wherein said first level shifting element is connected between said OR output and the gate of said source follower driver field effect transistor; and further comprising a second level shifting element connected between the source of said source follower driver field effect transistor and the gate of said output field effect transistor.

Claim 14

The circuit of claim 12, wherein said first and second level shifting elements each further comprises a level shifting diode.

Claim 15

The circuit of claim 13, wherein said level shifting diodes and said Schottky diodes further comprise GaAs diodes.

Claim 16

A logic circuit, comprising: a plurality of AND logic elements, each AND element including a plurality of Schottky diodes each having an anode and a cathode, with each cathode connected to a logic input and the anodes connected in common to establish an AND output; a diode pull up field effect transistor, having a source, a gate, and a drain, for each AND output, with the source connected to said AND output, the gate connected to the source, and the drain connected to a source of positive bias potential; an OR logic element, including a plurality of Schottky diodes each having an anode and a cathode, with each anode connected to one of said AND outputs and the cathodes connected in common to establish an OR output; a diode pull down field effect transistor, having a source, a gate, and a drain, with the source connected to a source of negative bias potential, the gate connected to the source, and the drain connected to said OR output; a level shifting diode connected between said OR output and the drain of said diode pull down field effect transistor; an output field effect transistor having a source, a gate, and a drain, with the gate connected to the drain of said diode pull down field effect transistor, the source connected to ground, and the drain providing a logic output from said circuit; and an output pull up field effect transistor having a source, a gate, and a drain, with the source connected to the drain of said output field effect transistor, the gate connected to the source, and the drain connected to said source of positive bias potential.

Claim 17

A logic circuit, comprising: a plurality of AND logic elements, each AND element including a plurality of Schottky diodes each having an anode and a cathode, with each cathode connected to a logic input and the anodes connected in common to establish an AND output; a diode pull up field effect transistor, having a source, a gate, and a drain, for each AND output, with the source connected to said AND output, the gate connected to the source, and the drain connected to a source of positive bias potential; an OR logic element, including a plurality of Schottky diodes each having an anode and a cathode, with each anode connected to one of said AND outputs and the cathodes connected in common to establish an OR output; a diode pull down field effect transistor, having a source, a gate, and a drain, with the source connected to a source of negative bias potential, the gate connected to the source, and the drain connected to said OR output; a level shifting diode connected between said OR output and the drain of said diode pull down field effect transistor; an output field effect transistor having a source, a gate, and a drain, with the gate connected to the drain of said diode pull down field effect transistor, the source connected to ground, and the drain providing a logic output from said circuit; and an output pull up field effect transistor having a source, a gate, and a drain, with the source connected to the drain of said output field effect transistor, the gate connected to the source, and the drain connected to said source of positive bias potential.

Claim 18

A logic circuit, comprising: a plurality of AND logic elements, each AND element including a plurality of Schottky diodes each having an anode and a cathode, with each cathode connected to a logic input and the anodes connected in common to establish an AND output; a diode pull up field effect transistor, having a source, a gate, and a drain, for each AND output, with the source connected to said AND output, the gate connected to the source, and the drain connected to a source of positive bias potential; an OR logic element, including a plurality of Schottky diodes each having an anode and a cathode, with each anode connected to one of said AND outputs and the cathodes connected in common to establish an OR output; a first level shifting diode connected to said OR output; a diode pull down field effect transistor, having a source, a gate, and a drain, with the source connected to a source of negative bias potential, the gate connected to the source, and the drain connected to said first level shifting diode; a source follower driver field effect transistor having a source, a gate, and a drain, with the gate connected to said OR output through said first level shifting diode and the drain connected to said source of negative bias potential; a second level shifting diode connected to the source of said source follower driver field effect transistor; a source follower pull down field effect transistor having a source, a gate, and a drain, with the source connected to said source of negative bias potential, the gate connected to the source, and the drain connected to the source of said source follower driver field effect transistor through said second level shifting diode; an output field effect transistor having a source, a gate, and a drain, with the source connected to ground, the gate connected to the drain of said source follower pull down field effect transistor, and the drain providing a logic output from said circuit; and an output pull up field effect transistor having a source, a gate, and a drain, with the source connected to the drain of said output field effect transistor, the gate connected to the source, and the drain connected to said source of positive bias potential.

Claim 19

A logic circuit, comprising: a plurality of AND logic elements, each AND element including a plurality of Schottky diodes each having an anode and a cathode, with each cathode connected to a logic input and the anodes connected in common to establish an AND output; a diode pull up field effect transistor, having a source, a gate, and a drain, for each AND output, with the source connected to said AND output, the gate connected to the source, and the drain connected to a source of positive bias potential; an OR logic element, including a plurality of Schottky diodes each having an anode and a cathode, with each anode connected to one of said AND outputs and the cathodes connected in common to establish an OR output; a first level shifting diode connected to said OR output; a diode pull down field effect transistor, having a source, a gate, and a drain, with the source connected to a source of negative bias potential, the gate connected to the source, and the drain connected to said first level shifting diode; a source follower driver field effect transistor having a source, a gate, and a drain, with the gate connected to said OR output through said first level shifting diode and the drain connected to said source of negative bias potential; a second level shifting diode connected to the source of said source follower driver field effect transistor; a source follower pull down field effect transistor having a source, a gate, and a drain, with the source connected to said source of negative bias potential, the gate connected to the source, and the drain connected to the source of said source follower driver field effect transistor through said second level shifting diode; an output field effect transistor having a source, a gate, and a drain, with the source connected to ground, the gate connected to the drain of said source follower pull down field effect transistor, and the drain providing a logic output from said circuit; and an output pull up field effect transistor having a source, a gate, and a drain, with the source connected to the drain of said output field effect transistor, the gate connected to the source, and the drain connected to said source of positive bias potential.