US4160918A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated logic circuit
Assignee: Individual
•
Filing: 1977-12-29
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Granted: 1979-07-10
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Expires: 1997-12-29
Abstract
Abstract An integrated injection logic circuit comprises a switching element using a unipolar FET whose gates are connected to the collectors of a load transistor. The emitter of the load transistor is connected to a power supply and the base area is combined with the source of the unipolar FET and grounded. Connected to the gates of the unipolar FET and to the base area of the load transistor are double-pole gating elements. The number of such elements is equal to the number of gates of the unipolar FET. The conduction voltage of the gating elements is lower than that across the p-n junctions of the respective gates of the unipolar FET.
Inventors
- 👤 Artashes R. Nazarian
- 👤 Vyacheslav Y. Kremlev
- 👤 Vilyam N. Kokin
- 👤 Nikolai M. Manzha
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:50
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09403; H03K19/09414; H03K19/082; H03K19/091; H03K19/09418; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H10D89/217
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
138 words
An integrated injection logic circuit comprising: a switching element having a unipolar FET with a plurality of gates, a source and a drain, said gates serving as inputs of said logic circuit and said drain serving as an output of said circuit; a load transistor having a plurality of collectors, an emitter and a base area, said transistor having its collectors connected to respective gates of said unipolar FET and said base area combined with said source of said unipolar FET and grounded; a power supply connected to said emitter of said load transistor; a plurality of double-pole gating elements connected to said gates of said unipolar FET and to said base area of said load transistor, the conduction voltage of said gating elements being lower than that across p-n junctions of respective gates of said unipolar FET.
Claim 2
Dependent Claim
138 words
An integrated injection logic circuit comprising: a switching element having a unipolar FET with a plurality of gates, a source and a drain, said gates serving as inputs of said logic circuit and said drain serving as an output of said circuit; a load transistor having a plurality of collectors, an emitter and a base area, said transistor having its collectors connected to respective gates of said unipolar FET and said base area combined with said source of said unipolar FET and grounded; a power supply connected to said emitter of said load transistor; a plurality of double-pole gating elements connected to said gates of said unipolar FET and to said base area of said load transistor, the conduction voltage of said gating elements being lower than that across p-n junctions of respective gates of said unipolar FET.
Claim 3
Dependent Claim
18 words
An integrated injection logic circuit according to claim 1, wherein said load transistor is a bipolar p-n-p transistor.
Claim 4
Dependent Claim
18 words
An integrated injection logic circuit according to claim 2, wherein said unipolar FET includes an n-type conduction channel.
Claim 5
Dependent Claim
17 words
An integrated injection logic circuit according to claim 3, wherein said double-pole gating elements are Schottky diodes.
Claim 6
Dependent Claim
17 words
An integrated injection logic circuit according to claim 2, wherein said double-pole gating elements are Schottky diodes.
Claim 7
Dependent Claim
18 words
An integrated injection logic circuit according to claim 1, wherein said unipolar FET includes an n-type conduction channel.
Claim 8
Dependent Claim
17 words
An integrated injection logic circuit according to claim 6, wherein said double-pole gating elements are Schottky diodes.
Claim 9
Dependent Claim
17 words
An integrated injection logic circuit according to claim 1, wherein said double-pole gating elements are Schottky diodes.
References Cited (Backward Citations)
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US3816758A
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US3916218A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-07-09 | 1983-01-08 | 1983-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-07-09 | 1987-01-08 | 1987-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-07-09 | 1991-01-08 | 1991-07-10 | $7700.00 | Window Closed / Lapsed |