Integrated power supply for merged transistor logic circuit

Claim 2

A monolithically integrated binary logic circuit for receiving first and second binary inputs respectively designated as x and y are providing a logical binary output of x+y, said logic circuit comprising: first, second, third and fourth transistors of a first conductivity type, said first, second, third and fourth transistors each having an emitter, base and collector; fifth, sixth seventh and eighth transistors of a second conductivity type, said second conductivity type being opposite to said first conductivity type, and said fifth, sixth, seventh and eighth transistors each having an emitter, base and collector; a first input terminal for receiving a first binary input designated as x and directly connected to said collector of said first transistor and said base of said fifth transistor; a second input terminal for receiving a second binary input designated as y and directly connected to said collector of said second transistor and said base of said sixth transistor; first means for applying a first potential on each of said emitters of said first, second, third and fourth transistors; first connection means connecting in common said bases of said first, second, third and fourth transistors, said collector of said seventh transistor and said emitters of said fifth, sixth, and eighth transistors; second connection means connecting said collector of said third transistor to said base of said seventh transistor; third connection means connecting said collector of said fourth transistor to said base of said eighth transistor; fourth connection means connecting said base of said seventh transistor to said collector of said eighth transistor; a first resistor connecting said collector of said third transistor to said emitter of said third transistor; a second resistor connecting said base of said fourth transistor to said collector of said fourth transistor; and an output terminal connected in common to said collector of said fifth transistor and said collector of said sixth transistor; said output terminal providing the logical binary output of x+y in response to binary inputs of x and y respectively impressed on said first and second input terminals.

Claim 3

A monolithically integrated binary logic circuit As recited in claim 1 wherein said first, second and third connections means respectively consist of an integral portion of the semiconductor material of which said monolithically integrated binary logic circuit is fabricated.

Claim 4

A monolithically integrated binary logic circuit as recited in claim 2 wherein said first means consists of a terminal adapted to receive said first potential and an integral portion of the semiconductor material of which said monolithically integrated binary logic circuit is fabricated.

Claim 5

A monolithically integrated binary logic circuit as recited in claim 1 wherein said first and second resistors respectively consist of an integral portion of the semiconductor material of which said monolithically integrated logic circuit is fabricated.

Claim 6

A monolithically integrated binary logic circuit as recited in claim 1 wherein said first and second resistors are respectively discrete resistors.

Claim 7

A monolithically integrated binary logic circuit as recited in claim 1 wherein said first input terminal is connected to said collector of said first transistor and said base of said fifth transistor by an integral portion of the semiconductor material of which said monolithically integrated binary logic circuit is fabricated; and said second input terminal is connected to said collector of said second transistor and said base of said sixth transistor by an integral portion of the semiconductor material of which said monolithically integrated binary logic circuit is fabricated.

Claim 8

A monolithically integrated binary logic circuit as recited in claim 1 wherein said first, second, third and fourth transistors are respectively laterally disposed within a monolithic semiconductor structure and said fifth, sixth, seventh and eighth transistors are respectively vertically disposed within said monolithic semiconductor structure.

Claim 9

A monolithically integrated binary logic circuit as recited in claim 7, wherein said bases of said first, second, third and fourth transistors; said emitters of said fifth, sixth and eighth transistors and said collector of said seventh transistor are respectively formed in common by a first portion of said monolithic semiconductor structure of a first conductivity type.

Claim 10

A monolithically integrated binary logic circuit as recited in claim 8 wherein said emitters of said first, second, third and fourth transistors are respectively formed in common by a second portion of said monolithic semi-conductor structure of a second conductivity type.

Claim 11

A monolithically integrated binary circuit as recited in claim 1, wherein said first, second, third, and fourth transistors are respectively vertically disposed within a monolithic semiconductor structure and said fifth, sixth, seventh and eighth transistors are respectively vertically disposed above said first, second third and fourth transistors in said monolithic structure.

Claim 12

A monolithic integrated binary circuit as recited in claim 10 wherein said bases of said first, second, third and fourth transistors; said emitters of said fifth, sixth and eighth transistors; and said collector of said seventh transistor are respectively formed in common by a first portion of said monolithic semiconductor structure of a first conductivity type.

Claim 13

A monolithic integrated binary logic circuit as recited in claim 11 wherein said emitters of said first, second, third and fourth transistors are respectively formed in common by a second portion of said monolithic structure of a second conductivity type.

Claim 14

A monolithic integrated binary logic circuit as recited in claim 1 wherein said first, second, third and fourth transistors are respectively laterally disposed with respect to each of said fifth, sixth, seventh and eighth transistors: and wherein said emitters of said first, second, third and fourth transistors are respectively formed in common by a first region of said first conductivity type; said collector of said firsT transistor and said base of said fifth transistor are formed in common by a second region of said first conductivity type; said collector of said second second transistor and said base of said sixth transistor are formed in common by a third region of said first conductivity type; said collector of said third transistor and said base of said seventh transistor are formed in common by a fourth region of said first conductivity type, said collector of said fourth transistor and said base of said eighth transistor are formed in common by a fifth region of said first conductivity type, and said bases of said first, second, third and fourth transistors; said collector of said seventh transistor; and said emitter of said fifth, sixth and eighth transistors are formed in common by a sixth region of said second conductivity type.

Claim 15

A monolithic integrated binary logic circuit as recited in claim 1, wherein said first, second, third and fourth transistors are respectively vertically disposed within a monolithic chip of semiconductor material and; said fifth, sixth, seventh and eighth transistors are respectively vertically disposed above said first, second, third and fourth transistors in said monolithic chip of semiconductor material.

Claim 16

A monolithic integrated binary logic circuit as recited in claim 14, wherein said emitters of said first, second, third and fourth transistors are respectively formed in common by a first region of said first conductivity type; said collector of said first transistor and said base of said fifth transistor are formed in common by a second region of said first conductivity type; said collector of said second transistor and said base of said sixth transistor are formed in common by a third region of said first conductivity type; said collector of said third transistor and said base of said seventh transistor are formed in common by a fourth region of said first conductivity type; said collector of said fourth transistor and said base of said eighth transistor are formed in common by a fifth region of said first conductivity type; and said bases of said first, second, third and fourth transistors; said collector of said seventh transistor; and said emitters of said fifth, sixth and eighth transistors are formed in common by a sixth region of said second conductivity type.

Claim 17

An integrated NOR circuit on a monolithic chip of semiconductor material of a first conductivity type having at least one planar surface; said monolithic chip of semiconductor material comprising: a first elongated region of a second conductivity type lying on and extending into said planar surface, second, third, fourth and fifth regions of a second conductivity type lying on and extending into said planar surfaces; said second, third, fourth and fifth regions being respectively positioned on said planar surface equi-distant from said first elongated region; a sixth region of said first conductivity lying on and extending into said planar surface; said sixth region being encompassed by said second region; a seventh region of said first conductivity lying on and extending into said planar surface; said seventh region being encompassed by said third region; an eighth region of said first conductivity lying on and extending into said planar surface; said eighth region being encompassed by said fourth region; a ninth region of said first conductivity lying on and extending into said planar surface; said ninth region being encompassed by said fifth region; first connection means for electrically connecting a first potential to said first elongated region; second connection means for electrically connecting a second potential to said eighth region; third connection means for electrically connecting said fourth region to said ninth region; a first resistor connected between said fifth region and said monolithic chip of semiconducTor material of said first conductivity type; a second resistor connected between said fourth region and said first elongated region; a first input terminal electrically connected to said second region; a second input terminal electrically connected to said third region; an output terminal electrically connected to said sixth and seventh regions; whereby when logical binary inputs x and y are respectively electrically impressed on said first and second input terminals the logical binary function x+y will be electrically manifested at said output terminal.

Claim 18

An integrated NOR circuit on a monolithic chip of semiconductor material of a first conductivity type having at least one planar surface; said monolithic chip of semiconductor material comprising: a first elongated region of a second conductivity type lying on and extending into said planar surface, second, third, fourth and fifth regions of a second conductivity type lying on and extending into said planar surfaces; said second, third, fourth and fifth regions being respectively positioned on said planar surface equi-distant from said first elongated region; a sixth region of said first conductivity lying on and extending into said planar surface; said sixth region being encompassed by said second region; a seventh region of said first conductivity lying on and extending into said planar surface; said seventh region being encompassed by said third region; an eighth region of said first conductivity lying on and extending into said planar surface; said eighth region being encompassed by said fourth region; a ninth region of said first conductivity lying on and extending into said planar surface; said ninth region being encompassed by said fifth region; first connection means for electrically connecting a first potential to said first elongated region; second connection means for electrically connecting a second potential to said eighth region; third connection means for electrically connecting said fourth region to said ninth region; a first resistor connected between said fifth region and said monolithic chip of semiconducTor material of said first conductivity type; a second resistor connected between said fourth region and said first elongated region; a first input terminal electrically connected to said second region; a second input terminal electrically connected to said third region; an output terminal electrically connected to said sixth and seventh regions; whereby when logical binary inputs x and y are respectively electrically impressed on said first and second input terminals the logical binary function x+y will be electrically manifested at said output terminal.

Claim 19

A monolithically integrated binary logic circuit as recited in claim 15 wherein said first and second resistors respectively consist essentially of an integral portion of the semiconductor material of which said monolithically integrated circuit is fabricated.

Claim 20

A monolithically integrated binary logic circuit as recited in claim 15 wherein said first and second resistors are respectively discrete resistors.

Claim 21

An integrated NOR circuit on a monolithic chip of semiconductor material of a first conductivity type having at least one planar surface, said integrated NOR circuit comprising: a buried region of a second conductivity type contained within said monolithic chip of semiconductor material; said buried region of said second conductivity type lying beneath, spaced from, and extending substantially parallel to said planar surface of said monolithic chip of semiconductor material of said first conductivity type; first, second, third and fourth discrete regions of said first conductivity type lying on and extending into said planar surface; fifth, sixth, seventh and eighth discrete regions of said second conductivity type; said fifth, sixth, seventh and eighth discrete regions lying on and extending into said planar surface; said fifth, sixth, seventh and eighth discrete regions respectively lying within said first, second, third and fourth regions; a ninth region of said second conductivity type lying on said planar surface and extending to said buried region of said second conductivity type; said ninth region encompassing on the planar surface of said monolithic chip said first, second, third and fourth discrete regions of said first conductivity type; a tenth region of said first conductivity type lying on and extending into said planar surface; said tenth region encompassing on the planar surface of said monolithic chip said ninth region; an eleventh region of said second conductivity type lying on and extending into said planar surface; said eleventh region encompassing on the planar surface of said monolithic chip said tenth region; first connection means for electrically connecting a first portion of said monolithic chip; where said first portion is beneath said buried region, to a first potential; second connection means for electrically connecting said seventh region to a second potential; third connection means connecting said third region to said eighth region; a first resistor electrically connected between said fourth region and said ninth region; a second resistor electrically connected between said third region and said first portion of said monolithic chip; a first input terminal electrically connected to said first region; a second input terminal electrically connected to said second region; an output terminal electrically connected to said fifth and sixth regions; whereby when logical binary inputs x and y are respectively electrically impressed on said first and second input terminals the logical binary function x+y will be electrically manifested at said output terminal.

Claim 22

An integrated NOR circuit on a monolithic chip of semiconductor material of a first conductivity type having at least one planar surface, said integrated NOR circuit comprising: a buried region of a second conductivity type contained within said monolithic chip of semiconductor material; said buried region of said second conductivity type lying beneath, spaced from, and extending substantially parallel to said planar surface of said monolithic chip of semiconductor material of said first conductivity type; first, second, third and fourth discrete regions of said first conductivity type lying on and extending into said planar surface; fifth, sixth, seventh and eighth discrete regions of said second conductivity type; said fifth, sixth, seventh and eighth discrete regions lying on and extending into said planar surface; said fifth, sixth, seventh and eighth discrete regions respectively lying within said first, second, third and fourth regions; a ninth region of said second conductivity type lying on said planar surface and extending to said buried region of said second conductivity type; said ninth region encompassing on the planar surface of said monolithic chip said first, second, third and fourth discrete regions of said first conductivity type; a tenth region of said first conductivity type lying on and extending into said planar surface; said tenth region encompassing on the planar surface of said monolithic chip said ninth region; an eleventh region of said second conductivity type lying on and extending into said planar surface; said eleventh region encompassing on the planar surface of said monolithic chip said tenth region; first connection means for electrically connecting a first portion of said monolithic chip; where said first portion is beneath said buried region, to a first potential; second connection means for electrically connecting said seventh region to a second potential; third connection means connecting said third region to said eighth region; a first resistor electrically connected between said fourth region and said ninth region; a second resistor electrically connected between said third region and said first portion of said monolithic chip; a first input terminal electrically connected to said first region; a second input terminal electrically connected to said second region; an output terminal electrically connected to said fifth and sixth regions; whereby when logical binary inputs x and y are respectively electrically impressed on said first and second input terminals the logical binary function x+y will be electrically manifested at said output terminal.

Claim 23

A monolithically integrated binary logic circuit as recited in claim 19 wherein said first and second resistors respectively consist essentially of an integral portion of the semiconductor material of which saiD monolithically integrated circuit is fabricated.

Claim 24

A monolithically integrated binary logic circuit as recited in claim 19 wherein said first and second resistors are respectively discrete resistors.

Claim 25

A monolithically integrated binary logic circuit for receiving at least one input and providing a logical binary output, said logic circuit comprising: first, second and third transistors of a first conductivity type; said first, second and third transistors each having an emitter, base and collector; fourth, fifth and sixth transistors of a second conductivity type, said second conductivity type being opposite to said first conductivity type, and said fourth, fifth and sixth transistors each having an emitter, base and collector; an input terminal for receiving a binary input and directly connected to said collector of said first transistor and said base of said fourth transistor; first means for applying a first potential on each of said emitters of said first, second and third transistors; first connection means connecting in common said bases of said first, second and third transistors, said collector of said fifth transistor and said emitters of said fourth and sixth transistors; second connection means connecting said collector of said second transistor to said base of said fifth transistor; third connection means connecting said collector of said third transistor to said base of said sixth transistor; fourth connection means connecting said base of said fifth transistor to said collector of said sixth transistor; a first resistor connecting said collector of said second transistor to said emitter of said second transistor; a second resistor connecting said base of said third transistor to said collector of said third transistor; and an output terminal connected to said collector of said fourth transistor for providing the logical binary output.

Claim 26

A monolithically integrated binary logic circuit for receiving at least one input and providing a logical binary output, said logic circuit comprising: first, second and third transistors of a first conductivity type; said first, second and third transistors each having an emitter, base and collector; fourth, fifth and sixth transistors of a second conductivity type, said second conductivity type being opposite to said first conductivity type, and said fourth, fifth and sixth transistors each having an emitter, base and collector; an input terminal for receiving a binary input and directly connected to said collector of said first transistor and said base of said fourth transistor; first means for applying a first potential on each of said emitters of said first, second and third transistors; first connection means connecting in common said bases of said first, second and third transistors, said collector of said fifth transistor and said emitters of said fourth and sixth transistors; second connection means connecting said collector of said second transistor to said base of said fifth transistor; third connection means connecting said collector of said third transistor to said base of said sixth transistor; fourth connection means connecting said base of said fifth transistor to said collector of said sixth transistor; a first resistor connecting said collector of said second transistor to said emitter of said second transistor; a second resistor connecting said base of said third transistor to said collector of said third transistor; and an output terminal connected to said collector of said fourth transistor for providing the logical binary output.

Claim 27

A monolithically integrated binary logic circuit as recited in claim 22 wherein said first, second and third connection means respectively consist of an integral portion of the semiconductor material of which said monolithically integrated binary logic circuit is fabricated.

Claim 28

A monolithically integrated binary logic circuit as recited in claim 23 wherein said first means consists of a terminal adapted to receive said first potential and an integral portion of the semiconductor material of which said monolithically integrated binary logic circuit is fabricated.

Claim 29

A monolithically integrated binary logic circuit as recited in claim 22 wherein said first and second resistors respectively consist of an integral portion of the semiconductor material of which said monolithically integrated logic circuit is fabricated.

Claim 30

A monolithically integrated binary logic circuit as recited in claim 22 wherein said first and second resistors are respectively discrete resistors.

Claim 31

A monolithically integrated binary logic circuit as recited in claim 22 wherein said input terminal is connected to said collector of said first transistor and said base of said fourth transistor by an integral portion of the semiconductor material of which said monolithically integrated binary logic circuit is fabricated.

Claim 32

A monolithically integrated binary logic circuit as recited in claim 22 wherein said first, second and third transistors are respectively laterally disposed within a monolithic semiconductor structure and said fourth, fifth and sixth transistors are respectively vertically disposed within said monolithic semiconductor structure.

Claim 33

A monolithically integrated binary logic circuit as recited in claim 28, wherein said bases of said first, second and third transistors; said emitters of said fourth and sixth transistors, and said collector of said fifth transistor are respectively formed in common by a first portion of said monolithic semiconductor structure of a first conductivity type.

Claim 34

A monolithically integrated binary logic cirCuit as recited in claim 29 wherein said emitters of said first, second and third transistors are respectively formed in common by a second portion of said monolithic semiconductor structure of a second conductivity type.

Claim 35

A monolithically integrated binary circuit as recited in claim 22, wherein said first, second and third transistors are respectively vertically disposed within a monolithic semiconductor structure, and said fourth, fifth and sixth transistors are respectively vertically disposed above said first second and third transistors in said monolithic structure.

Claim 36

a monolithic integrated binary circuit as recited in claim 31, wherein said bases of said first, second and third transistors; said emitters of said fourth and sixth transistors; and said collector of said fifth transistor are respectively formed in common by a first portion of said monolithic semiconductor structure of a first conductivity type.

Claim 37

A monolithic integrated binary logic circuit as recited in claim 32, wherein said emitters of said first, second and third transistors are respectively formed in common by a second portion of said monolithic structure of a second conductivity type.

Claim 38

A monolithic integrated binary logic circuit as recited in claim 22, wherein said first, second and third transistors are respectively laterally disposed with respect to each of said fourth, fifth and sixth transistors; and wherein said emitters of said first, second and third transistors are respectively formed in common by a first region of said first conductivity type; said collector of said first transistor and said base of said fourth transistor are formed in common by a second region of said first conductivity type; said collector of said second transistor and said base of said fifth transistor are formed in common by a third region of said first conductivity type, said collector of said third transistor and said base of said sixth transistor are formed in common by a fourth region of said first conductivity type, and said bases of said first, second and third transistors, said collector of said fifth transistor, and said emitters of said fourth and sixth transistors are formed in common by a fifth region of said second conductivity type.

Claim 39

A monolithic integrated binary logic circuit as recited in claim 22, wherein said first, second and third transistors are respectively vertically disposed within a monolithic chip of semiconductor material and; said fourth, fifth and sixth transistors are respectively vertically disposed above said first, second and third transistors in said monolithic chip of semiconductor material.

Claim 40

A monolithic integrated binary logic circuit as recited in claim 35, wherein said emitters of said first, second and third transistors are respectively formed in common by a first region of said first conductivity type; said collector of said first transistor and said base of said fourth transistor are formed in common by a second region of said first conductivity type; said collector of said second transistor and said base of said fifth transistor are formed in common by a third region of said first conductivity type; said collector of said third transistor and said base of said sixth transistor are formed in common by a fourth region of said first conductivity type; and said bases of said first, second and third transistors, said collector of said fifth transistor, and said emitters of said fourth and sixth transistors are formed in common by a fifth region of said second conductivity type.