US4035664A
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US
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Current hogging injection logic
Assignee: International Business Machines Corp
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Filing: 1975-09-15
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Granted: 1977-07-12
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Expires: 1995-09-15
Abstract
Abstract The disclosure is directed to the circuitry and monolithic semiconductor structure of Current Hogging Injection Logic Configurations. More specifically the disclosure relates to a semiconductor arrangement for the basic components of a highly integratable, logic semiconductor circuit concept predicated on multicollector inverter transistors which are fed by means of a carrier injection into their emitter/base zones.
Inventors
- 👤 Horst H. Berger
- 👤 Siegfried K. Wiedmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:21
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D84/63
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
411 words
A monolithically integrated binary logic circuit for receiving first, second and third binary inputs respectively designated as x, y and z and providing a first logical binary output of x, a second logical binary output of x .sup.. y, and a third logical binary output of x .sup.. y .sup.. 2, said logic circuit comprising: first, second and third transistors of a first conductivity type, said first, second and third transistors each having an emitter, base and collector; fourth, fifth and sixth transistors of a second conductivity type, said second conductivity type being opposite to said first conductivity type, said fourth, fifth and sixth transistors each having an emitter, base and collector; a first input terminal for receiving a first binary input designated as x and directly connected to said collector of said first transistor, said emitter of said second transistor and said base of said fourth transistor; a second input terminal for receiving a second binary input designated as y and directly connected to said collector of said second transistor, said emitter of said third transistor and said base of said fifth transistor; a third input terminal for receiving a third binary input designated as z and directly connected to said collector of said third transistor and said base of said sixth transistor; current source means connected to said emitter of said first transistor; first connection means connecting in common said base of said first transistor, said base of said second transistor, said base of said third transistor, said emitter of said fourth transistor, said emitter of said fifth transistor, and said emitter of said sixth transistor; second connection means connecting said first connection means to a source of reference potential; a first output terminal connected to said collector of said fourth transistor, said first output terminal providing the logical binary output of x in response to the binary input x being impressed on said first input terminal; a second output terminal connected to said collector of said fifth transistor, said second output terminal providing the logical binary output of x .sup.. y in response to binary inputs of x and y respectively being impressed on said first and second input terminals; and a third output terminal connected to said collector of said sixth transistor, said third output terminal providing the logical binary output x .sup.. y .sup.. z in response to binary inputs of x, y and z respectively being impressed on said first, second and third input terminals.
Claim 2
Dependent Claim
411 words
A monolithically integrated binary logic circuit for receiving first, second and third binary inputs respectively designated as x, y and z and providing a first logical binary output of x, a second logical binary output of x .sup.. y, and a third logical binary output of x .sup.. y .sup.. 2, said logic circuit comprising: first, second and third transistors of a first conductivity type, said first, second and third transistors each having an emitter, base and collector; fourth, fifth and sixth transistors of a second conductivity type, said second conductivity type being opposite to said first conductivity type, said fourth, fifth and sixth transistors each having an emitter, base and collector; a first input terminal for receiving a first binary input designated as x and directly connected to said collector of said first transistor, said emitter of said second transistor and said base of said fourth transistor; a second input terminal for receiving a second binary input designated as y and directly connected to said collector of said second transistor, said emitter of said third transistor and said base of said fifth transistor; a third input terminal for receiving a third binary input designated as z and directly connected to said collector of said third transistor and said base of said sixth transistor; current source means connected to said emitter of said first transistor; first connection means connecting in common said base of said first transistor, said base of said second transistor, said base of said third transistor, said emitter of said fourth transistor, said emitter of said fifth transistor, and said emitter of said sixth transistor; second connection means connecting said first connection means to a source of reference potential; a first output terminal connected to said collector of said fourth transistor, said first output terminal providing the logical binary output of x in response to the binary input x being impressed on said first input terminal; a second output terminal connected to said collector of said fifth transistor, said second output terminal providing the logical binary output of x .sup.. y in response to binary inputs of x and y respectively being impressed on said first and second input terminals; and a third output terminal connected to said collector of said sixth transistor, said third output terminal providing the logical binary output x .sup.. y .sup.. z in response to binary inputs of x, y and z respectively being impressed on said first, second and third input terminals.
Claim 3
Dependent Claim
64 words
A monolithically integrated binary logic chip fabricated by large scale integration techniques, said chip containing at least first and second monolithically integrated binary logic circuits as recited in claim 1, wherein the first output terminal of said first monolithically integrated binary logic circuit is connected via at least one Schottky diode to the first input terminal of said second monolithically integrated binary logic circuit.
Claim 4
Dependent Claim
70 words
A monolithically integrated binary logic circuit as recited in claim 1 wherein a first Schottky Barrier diode is connected between said first output terminal and said collector of said fourth transistor, a second Schottky Barrier diode is connected between said second output terminal and said collector of said fifth transistor, and a third Schottky Barrier diode is connected between said third output terminal and said collector of said sixth transistor.
Claim 5
Dependent Claim
50 words
A monolithically integrated binary logic circuit, as recited in claim 1 wherein said fourth transistor has a plurality of collectors and each of said collectors of said fourth transistor provides the logical binary output x in response to a binary input of x being impressed on said first input terminal.
Claim 6
Dependent Claim
56 words
A monolithically integrated binary logic circuit as recited in claim 1 wherein said fifth transistor has a plurality of collectors and each of said collectors of said fifth transistor provides the logical binary output x .sup.. y in response to binary inputs of x and y respectively being impressed on said first and second input terminals.
Claim 7
Dependent Claim
60 words
A monolithically integrated binary logic circuit as recited in claim 1 wherein said sixth transistor has a plurality of collectors and each of said collectors of said sixth transistor provides the logical binary output x .sup.. y .sup.. z in response to binary inputs of x, y and z respectively being impressed on said first, second and third input terminals.
Claim 8
Dependent Claim
43 words
A monolithically integrated binary logic circuit as recited in claim 1 wherein said first, second and third transistors are respectively laterally disposed within a monolithic semiconductor structure and said fourth, fifth and sixth transistors are respectively vertically disposed within said monolithic semiconductor structure.
Claim 9
Dependent Claim
68 words
A monolithically integrated binary logic circuit as recited in claim 7 wherein said base of said first transistor, said base of said second transistor said base of said third transistor, said emitter of said fourth transistor, said emitter of said fifth transistor, and said emitter of said sixth transistor are respectively formed in common by a first portion of said monolithic semiconductor structure of a first conductivity type.
Claim 10
Dependent Claim
50 words
A monolithically integrated binary logic circuit as recited in claim 8 wherein said collector of said first transistor, said base of said fourth transistor and said emitter of said second transistor are respectively formed in common by a second portion of said monolithic semiconductor structure of a second conductivity type.
Claim 11
Dependent Claim
50 words
A monolithically integrated binary logic circuit as recited in claim 9 wherein said collector of said second transistor, said base of said fifth transistor and said emitter of said third transistor are respectively formed in common by a third portion of said monolithic semiconductor structure of said second conductivity type.
Claim 12
Dependent Claim
44 words
A monolithically integrated binary logic circuit as recited in claim 10 wherein said collector of said third transistor and said base of said sixth transistor are respectively formed in common by a fourth portion of said monolithic semiconductor structure of said second conductivity type.
Claim 13
Dependent Claim
59 words
A monolithically integrated binary logic circuit as recited in claim 1 wherein said first input terminal, said collector of said first transistor, said base of said fourth transistor and said emitter of said second transistor are respectively formed in common by a first integral portion of the semiconductor material of which said monolithically integrated binary logic circuit is fabricated.
Claim 14
Dependent Claim
59 words
A monolithically integrated binary logic circuit as recited in claim 1 wherein said second input terminal, said collector of said second transistor, said base of said fifth transistor, and said emitter of said third transistor are respectively formed in common by a second integral portion of the semiconductor material of which said monolithically integrated binary logic circuit is fabricated.
Claim 15
Dependent Claim
53 words
A monolithically integrated binary logic circuit as recited in claim 1 wherein said third input terminal, said collector of said third transistor and said base of said sixth transistor are respectively formed in common by a third integral portion of the semiconductor material of which said monolithically integrated binary logic circuit is fabricated.
Claim 16
Dependent Claim
67 words
A monolithically integrated binary logic circuit as recited in claim 1 wherein said first connection means, said transistor, said base of said third transistor said emitter of said fourth transistor, said emitter of said fifth transistor, and said emitter of said sixth transistor are respectively formed in common by a fourth integral portion of the semiconductor material of which said monolithically integrated binary logic circuit is fabricated.
Claim 17
Dependent Claim
183 words
A monolithically integrated binary logic circuit as recited in claim 1 wherein said current source means connected to said emitter of said first transistor impresses a binary input designated as q on said emitter of said first transistor, whereby said binary logic circuit, as recited in claim 110, provides the logical binary output x .sup.. q at said first output terminal in response to the binary inputs of x and q respectively being impressed on said first input terminal and said emitter of said first transistor, provides the logical binary output x .sup.. y .sup.. q at said second output terminal in response to the binary inputs of x, y and q respectively being impressed on said first input terminal, said second input terminal and said emitter of said first transistor, and provides the logical binary output x .sup.. y .sup.. z .sup.. q at said third output terminal in response to the binary inputs x, y, z and q respectively being impressed on said first input terminal, said second input terminal, said third input terminal and said emitter of said first transistor.
Claim 18
Dependent Claim
193 words
A monolithically integrated binary logic circuit as recited in claim 1 wherein: said base of said first transistor, said base of said second transistor, said base of said third transistor, said emitter of said fourth transistor, said emitter of said fifth transistor and said emitter of said sixth transistor are respectively formed in common by a first portion of the semiconductor material of which said monolithic integrated binary logic circuit is fabricated; said collector of said first transistor, said base of said fourth transistor and said emitter of said second transistor are respectively formed in common by a second portion of the semiconductor material of which said monolithic integrated binary logic circuit is fabricated; said collector of said second transistor, said base of said fifth transistor and said emitter of said third transistor are respectively formed in common by a third portion of the semiconductor material of which said monolithic integrated binary logic circuit is fabricated; and said collector of said third transistor and said base of said sixth transistor are respectively formed in common by a fourth portion of the semiconductor material of which said monolithic integrated binary logic circuit is fabricated.
Claim 19
Dependent Claim
386 words
An integrated binary logic circuit for providing a first binary logical output of x, a second binary logical output of x .sup.. y, and a third binary logical output of x .sup.. y .sup.. z of first, second and third binary inputs respectively designated as x, y and z, said integrated binary logic circuit being contained on a monolithic chip of semiconductor material of a first conductivity type having at least one planar surface, said integrated binary logic circuit comprising: first, second, third and fourth discrete regions respectively of a second conductivity type lying on and extending into said planar surface of said monolithic chip, said first, second, third and fourth discrete regions being spaced apart one from another in the order recited on said planar surface; a fifth discrete region of said first conductivity type lying on and extending into said planar surface, said fifth discrete region being contained within and encompassed by said second discrete region; a sixth discrete region of said first conductivity type lying on and extending into said planar surface, said sixth discrete region being contained within and encompassed by said third discrete region; a seventh discrete region of said first conductivity type lying on and extending into said planar surface, said seventh discrete region being contained within and encompassed by said third discrete region; first means for impressing an input current on said first discrete region; second means for impressing the binary input x on said second discrete region; third means for impressing the binary input y on said third discrete region; fourth means for impressing the binary input z on said fourth discrete region; fifth means for impressing a reference potential on said monolithic chip of semiconductor material of said first conductivity type; first output means electrically contacting said fifth discrete region; second output means electrically contacting said sixth region; and third output means electrically contacting said seventh discrete region, whereby the logical binary outputs x, x .sup.. y and x .sup.. y .sup.. z are respectively manifested by said first output means, said second output means and said third output means in response to said second means, said third means and said fourth means respectively impressing said binary inputs x, y and z on said second discrete region, said third discrete region and said fourth discrete region, respectively.
Claim 20
Dependent Claim
386 words
An integrated binary logic circuit for providing a first binary logical output of x, a second binary logical output of x .sup.. y, and a third binary logical output of x .sup.. y .sup.. z of first, second and third binary inputs respectively designated as x, y and z, said integrated binary logic circuit being contained on a monolithic chip of semiconductor material of a first conductivity type having at least one planar surface, said integrated binary logic circuit comprising: first, second, third and fourth discrete regions respectively of a second conductivity type lying on and extending into said planar surface of said monolithic chip, said first, second, third and fourth discrete regions being spaced apart one from another in the order recited on said planar surface; a fifth discrete region of said first conductivity type lying on and extending into said planar surface, said fifth discrete region being contained within and encompassed by said second discrete region; a sixth discrete region of said first conductivity type lying on and extending into said planar surface, said sixth discrete region being contained within and encompassed by said third discrete region; a seventh discrete region of said first conductivity type lying on and extending into said planar surface, said seventh discrete region being contained within and encompassed by said third discrete region; first means for impressing an input current on said first discrete region; second means for impressing the binary input x on said second discrete region; third means for impressing the binary input y on said third discrete region; fourth means for impressing the binary input z on said fourth discrete region; fifth means for impressing a reference potential on said monolithic chip of semiconductor material of said first conductivity type; first output means electrically contacting said fifth discrete region; second output means electrically contacting said sixth region; and third output means electrically contacting said seventh discrete region, whereby the logical binary outputs x, x .sup.. y and x .sup.. y .sup.. z are respectively manifested by said first output means, said second output means and said third output means in response to said second means, said third means and said fourth means respectively impressing said binary inputs x, y and z on said second discrete region, said third discrete region and said fourth discrete region, respectively.
Claim 21
Dependent Claim
26 words
An integrated binary logic circuit, as recited in claim 18, where said first, second and third output means, respectively include at least one Schottky Barrier diode.
Claim 22
Dependent Claim
25 words
An integrated binary logic circuit, as recited in claim 18, where said second, third and fourth means respectively include at least one Schottky Barrier diode.
Claim 23
Dependent Claim
45 words
An integrated binary logic circuit, as recited in claim 18 where said first, second and third output means, respectively include at least one Schottky metal contact forming a Schottky Barrier diode junction with the discrete region with which said output means is in electrical contact.
Claim 24
Dependent Claim
45 words
An integrated binary logic circuit, as recited in claim 18, where said second, third and fourth means respectively include at least one Schottky metal contact forming a Schottky Barrier diode junction with the discrete region with which said second, third and fourth means is associated.
Claim 25
Dependent Claim
58 words
An integrated binary logic circuit, as recited in claim 18, wherein an eighth discrete region of said first conductivity type is provided lying on and extending into said planar surface, said eighth discrete region being contained within and encompassed by said second discrete region, a Schottky metal contact forming a Schottky Barrier junction with said eighth discrete region.
Claim 26
Dependent Claim
44 words
An integrated binary logic circuit, as recited in claim 18 wherein said second output means electrically contacting said sixth discrete region comprises at least one discrete ohmic contact with said sixth region and at least one discrete Schottky metal contact with said sixth region.
Claim 27
Dependent Claim
55 words
An integrated binary logic circuit as recited in claim 18, wherein said first conductivity type is N type semiconductor material and said second conductivity type is P type semiconductor material, and where said fourth means includes a Schottky metal contact overlying said pn junction existing between said fourth discrete region and said seventh discrete region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-11 | 1981-01-10 | 1981-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-11 | 1985-01-10 | 1985-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-11 | 1989-01-10 | 1989-07-12 | $7700.00 | Window Closed / Lapsed |