Bistable logic circuit using field effect transistors with a low voltage threshold and storage device incorporating such a circuit

Claim 2

A bistable logic circuit using field effect transistors with a low threshold voltage connected between first and second terminals of a supply voltage generator, comprising first, second and third field effect transistors, said first and second field effect transistors being in series with their gates interconnected and connected to the first terminal of the supply voltage generator by a first load, the source of the first field effect transistor being connected to the second terminal of the supply voltage generator, the drain of the first field effect transistor being connected to the source of the second field effect transistor, the drain of the second field effect transistor being connected on the one hand to the first terminal of the supply voltage generator by a second load and on the other hand to the gate of the third field effect transistor, whose drain is connected to the first terminal of the supply voltage generator and whose source is connected via a Schottky diode to the common point constituted by the drain of the first transistor and by the source of the second transistor, said common point constituting the output terminal of the bistable circuit.

Claim 3

A bistable circuit according to claim 1, which also comprises a Schottky diode polarized in the conductive direction inserted between the source of the first transistor and the second terminal of the supply voltage generator.

Claim 4

A storage device comprising memory cells, each one of said memory cells comprising: a supply voltage generator having first and second terminals; first and second field effect transistors the source of the second transistor being connected to the drain of the first field effect transistor, the gates of said first and second field effect transistors being interconnected and connected to said first terminal by a first load, the source of the first field effect transistor being connected to said second terminal, and the drain of the second field effect transistor being connected to said first terminal by a second load; a first Schottky diode; a third field effect transistor, having its gate connected to the drain of said second field effect transistor, its drain connected to said first terminal and its source connected via said first Schottky diode to the common point constituted by the drain of the first transistor and by the source of the second transistor, said common point constituting an output terminal; and a second Schottky diode polarized in the conductive direction and inserted between the source of the first field effect transistor and said second terminal.

Claim 5

A storage device comprising memory cells, each one of said memory cells comprising: a supply voltage generator having first and second terminals; first and second field effect transistors the source of the second transistor being connected to the drain of the first field effect transistor, the gates of said first and second field effect transistors being interconnected and connected to said first terminal by a first load, the source of the first field effect transistor being connected to said second terminal, and the drain of the second field effect transistor being connected to said first terminal by a second load; a first Schottky diode; a third field effect transistor, having its gate connected to the drain of said second field effect transistor, its drain connected to said first terminal and its source connected via said first Schottky diode to the common point constituted by the drain of the first transistor and by the source of the second transistor, said common point constituting an output terminal; and a second Schottky diode polarized in the conductive direction and inserted between the source of the first field effect transistor and said second terminal.

Claim 6

A storage device according to claim 3, wherein the memory cells form a matrix having addressing rows and columns, respectively X and Y, and corresponding addressing circuits X and Y permitting the selection of a desired cell.

Claim 7

A storage device according to claim 4, wherein the addressing circuit X comprises a fourth field effect transistor for selecting the memory cell, the drain of said fourth transistor being connected to an output point of the cell, while its gate is connected to an addressing row in X.

Claim 8

A storage device according to claim 5, wherein the addressing circuit Y comprises a fifth field effect transistor for selecting the memory cell, the drain of said fifth transistor being connected to the source of said fourth transistor, the gate of said fifth transistor being connected to an addressing column in Y.

Claim 9

A storage device according to claim 6, wherein the fourth and fifth field effect transistors are combined into a single bigate selection field effect transistor, one of the gates being connected to the addressing row at X and the other gate to the addressing column at Y.

Claim 10

A storage device according to claim 7, comprising a read-write mode selection device, said device being connected at its output to the gate of a transistor, whose drain is connected either to the source of said fifth field effect transistor or to the source of a bigate field effect transistor.

Claim 11

A storage device according to claim 8 wherein the read-write selection device is a logic reversing switch.

Claim 12

A storage device according to claim 7, comprising a reading circuit connected at the input to the drain of a transistor, which is also connected either to the source of said fifth field effect transistor, or to the source of a bigate field effect transistor.

Claim 13

A storage device according to claim 10, wherein the read circuit comprises two stages, the first stage being a following-displacing stage, while the second stage is a logic reversing switch.

Claim 14

A storage device according to claim 7, wherein each addressing circuit at X or Y comprises an NOR gate having several inputs and an output connected either to the drain of a selection transistor at X or Y, or to the drain of the bigate field effect transistor.

Claim 15

A storage device according to claim 12, wherein the inputs of the NOR gates are controlled by control circuits making it possible to select the desired row number and the desired column number.

Claim 16

A storage device according to claim 13, wherein these control circuits comprise two identical circuits, each circuit incorporating an input reversing stage, the output stage being comprised by a field effect transistor with two independent sources.