US4697110A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fluctuation-free input buffer
Assignee: Hitachi Ltd
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Filing: 1983-11-28
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Granted: 1987-09-29
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Expires: 2003-11-28
Abstract
Abstract An input buffer for a semiconductor circuit is provided with a source follower circuit composed of a first FET whose gate electrode has an input connected thereto, and a second FET of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET directly or through at least one level-shifting diode and whose gate electrode is supplied with a control voltage. The input buffer also includes a FET inverter circuit connected to the drain electrode of the second FET directly or through at least one level-shifting diode. An output signal for the input buffer is derived from the FET inverter circuit. A particular advantage of the present invention is that it permits the input buffer to switch its output from one level to another in response to input signals falling within a predetermined voltage range regardless of logic threshold level fluctuations in the FETs and fluctuations in supply voltages coupled to the input buffer.
Inventors
- 👤 Noboru Masuda
- 👤 Michio Asano
- 👤 Takehisa Hayashi
- 👤 Hirotoshi Tanaka
- 👤 Akira Masaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:05
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0952; H03K19/003; H03K19/00369; H03K19/00384; H03K19/01; H03K19/017; H03K19/01707; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018535
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
139 words
An input buffer comprising a source follower circuit having a logic threshold level which is subject to undesired fluctuations in logic threshold level which includes first and second FETs of an identical conductivity type connected in series, and in which a gate of said first FET is connected to a circuit input for receiving an input signal, and a FET inverter circuit, which receives an output of said source follower circuit derived from between said first and second FETs wherein the logic threshold level of said source follower circuit is controlled by a voltage which is produced by a means for producing a compensating voltage which varies in a manner opposite to the undesired fluctuations in logic threshold level, that is applied to a gate of said second FET in said source follower circuit to cancel said undesired fluctuations.
Claim 2
Dependent Claim
139 words
An input buffer comprising a source follower circuit having a logic threshold level which is subject to undesired fluctuations in logic threshold level which includes first and second FETs of an identical conductivity type connected in series, and in which a gate of said first FET is connected to a circuit input for receiving an input signal, and a FET inverter circuit, which receives an output of said source follower circuit derived from between said first and second FETs wherein the logic threshold level of said source follower circuit is controlled by a voltage which is produced by a means for producing a compensating voltage which varies in a manner opposite to the undesired fluctuations in logic threshold level, that is applied to a gate of said second FET in said source follower circuit to cancel said undesired fluctuations.
Claim 3
Dependent Claim
48 words
An input buffer according to claim 1, wherein said source follower circuit includes at least one first diode which is connected in series between said first and second FETs, and the output of said source follower circuit is derived from between said second FET and said first diode.
Claim 4
Dependent Claim
60 words
An input buffer according to claim 1, wherein said FET inverter circuit includes a first load element and a third FET which are connected in series, wherein a gate of said third FET receives the output of said source follower circuit, and wherein an output of said inverter is provided from between said first load element and said third FET.
Claim 5
Dependent Claim
24 words
An input buffer according to claim 3, wherein said first load element is a fourth FET those source and gate are connected in common.
Claim 6
Dependent Claim
31 words
An input buffer according to claim 1, further comprising a capacitor which is connected between the input end of said source follower circuit and an input end of said FET inverter.
Claim 7
Dependent Claim
94 words
An input buffer according to claim 1, wherein said means for producing a compensating voltage includes a first circuit which receives a predetermined reference voltage and which is equivalent to said source follower circuit, a second circuit which receives an output of said first circuit and which is equivalent to said FET inverter circuit, and an inverter circuit which receives an output of said second circuit; an output of said inverter circuit being fed back to said first circuit and being supplied to the gate of said second FET of said source follower circuit.
Claim 8
Dependent Claim
30 words
An input buffer according to claim 6, wherein the output of said inverter circuit in said said means for producing a compensating voltage is derived through at least one diode.
Claim 9
Dependent Claim
23 words
An input buffer according to claim 6, wherein said second circuit receives the output of said first circuit through at least one diode.
Claim 10
Dependent Claim
77 words
An input buffer according to claim 4, wherein the respective FETs which constitute said source follower circuit and said FET inverter circuit have equal threshold voltages, and wherein a sum between a square root of a gate width ratio of said first and second FETs of said source follower circuit and a square root of an inverse number of a gate width ratio of said third and fourth FETs of said FET inverter circuit is approximately 2.
Claim 11
Dependent Claim
70 words
An input buffer according to claim 6, wherein said means for producing a compensating voltage comprises means for adjusting the voltage supplied to the gate of said second FET so that an output of said FET inverter circuit will completely switch from a first predetermined level to a second predetermined level in response to input signals applied to said gate of said first FET falling within a predetermined voltage range.
Claim 12
Dependent Claim
42 words
An input buffer according to claim 10, wherein said input signals applied to said gate of said first FET are derived from an ECL LSI circuit, and wherein said output of said FET inverter circuit is coupled to a FET LSI circuit.
Claim 13
Dependent Claim
40 words
An input buffer according to claim 11, wherein said predetermined voltage range for said input signals applied to said gate of said first FET for completely switching said output of said FET inverter circuit is -1.15 V to -1.45 V.
Claim 14
Dependent Claim
98 words
An input buffer comprising a source follower circuit which includes first and second FETs of an identical conductivity type connected in series, and in which a gate of said first FET is connected to a circuit input for receiving an input signal, and a FET inverter circuit which receives an output of said source follower circuit derived from between said first and second FETs, through at least one diode, a logic threshold level of said source follower circuit being controlled by a voltage which is supplied to a gate of said second FET in said source follower circuit.
Claim 15
Dependent Claim
98 words
An input buffer comprising a source follower circuit which includes first and second FETs of an identical conductivity type connected in series, and in which a gate of said first FET is connected to a circuit input for receiving an input signal, and a FET inverter circuit which receives an output of said source follower circuit derived from between said first and second FETs, through at least one diode, a logic threshold level of said source follower circuit being controlled by a voltage which is supplied to a gate of said second FET in said source follower circuit.
Claim 16
Dependent Claim
145 words
An input buffer comprising a source follower circuit which includes first and second FETs of an identical conductivity type connected in series, and in which a gate of said first FET is connected to a circuit input for receiving an input signal, and a FET inverter circuit which receives an output of said source follower circuit, said source follower circuit including at least one first diode which is connected in series between said first and second FETs, and the output of said source follower circuit being derived from between said second FET and said first diode and wherein said FET inverter circuit receives the output of said source follower circuit through at least one second diode, a logic threshold level of said source follower circuit being controlled by a voltage which is supplied to a gate of said second FET in said source follower circuit.
Claim 17
Dependent Claim
145 words
An input buffer comprising a source follower circuit which includes first and second FETs of an identical conductivity type connected in series, and in which a gate of said first FET is connected to a circuit input for receiving an input signal, and a FET inverter circuit which receives an output of said source follower circuit, said source follower circuit including at least one first diode which is connected in series between said first and second FETs, and the output of said source follower circuit being derived from between said second FET and said first diode and wherein said FET inverter circuit receives the output of said source follower circuit through at least one second diode, a logic threshold level of said source follower circuit being controlled by a voltage which is supplied to a gate of said second FET in said source follower circuit.
References Cited (Backward Citations)
US3299291A
Cited
JPS50743A
Cited
US4023050A
Cited
US4242604A
Cited
US4393315A
Cited
US4453095A
Cited
US4496856A
Cited
US4563601A
Cited
US4558235A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-28 | 1991-03-30 | 1991-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-28 | 1995-03-30 | 1995-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-28 | 1999-03-30 | 1999-09-29 | $7700.00 | Window Closed / Lapsed |