Level conversion input circuit

Claim 2

A level conversion circuit including: a first input circuit comprising at least a first MOS transistor having a first terminal, a second terminal and a gate terminal, and a second MOS transistor which has a channel of opposite conductivity type to said first MOS transistor and which has a first terminal, a second terminal and a gate terminal, wherein said gate terminal of said first MOS transistor is coupled to the input of said first input circuit for receiving an input signal, said first terminal of said first MOS transistor is coupled to a first voltage source, said second terminal of said first MOS transistor is coupled to said second terminal of said second MOS transistor, said first terminal of said second MOS transistor is coupled to a second voltage source, and an output of said first input circuit is taken out from said second terminal of said first MOS transistor; and a voltage generation circuit applying a voltage to the gate terminal of said second MOS transistor of said first input circuit, wherein the voltage from said voltage generation circuit controls the logic threshold voltage of said first input circuit.

Claim 3

The level conversion input circuit as defined in claim 1 wherein said first input circuit includes a first load connected in series with said second MOS transistor.

Claim 4

The level conversion input circuit as defined in claim 1 wherein said voltage generator circuit comprises a second input circuit which receives a first reference voltage as its input and which comprises at least a third MOS transistor having a first terminal, a second terminal and a gate terminal, and fourth MOS transistor which has a channel of opposite conductivity type to said third MOS transistor and has a first terminal, a second terminal and a gate terminal, wherein said gate terminal of said third MOS transistor is coupled to receive said first reference voltage, said first terminal of said third MOS transistor is coupled to said first voltage source, said second terminal of said third MOS transistor is coupled to said second terminal of said fourth MOS transistor, said first terminal of said fourth MOS transistor is coupled to said second voltage source and an output of said second input circuit is taken out from said second terminal of said third MOS transistor, and an amplification circuit of at least one stage which receives the output of said second input circuit and a second reference voltage as its inputs and amplifies the difference between these voltages, wherein the output of said amplification circuit is the output of said voltage generation circuit.

Claim 5

The level conversion input circuit as defined in claim 3 wherein said control voltage generation circuit has a voltage division circuit for generating said second reference voltage.

Claim 6

The level conversion input circuit as defined in claim 3 wherein said amplification circuit comprises a differential amplifier which receives the output of said second input circuit and said second reference voltage as its input.

Claim 7

The level conversion input circuit as defined in claim 5 wherein said differential amplifier comprises fifth and sixth MOS transistors having gates which are coupled to receive the output of said second input circuit and said second reference voltage, respectively, a constant current source providing a constant current to both of said fifth and sixth MOS transistors and a load connected to at least one of said fifth and sixth MOS transistors, and wherein the output of said differential amplifier is taken out from between either one of said fifth and sixth MOS transistors and said load.

Claim 8

The level conversion input circuit as defined in claim 3 wherein said amplification circuit is comprised of a differential amplifier which receives the output of said second input circuit and said second reference voltage as its inputs, and an amplifier which amplifies the output of said differential amplifier.

Claim 9

The level conversion input circuit as defined in claim 7 wherein said amplifier comprises a fifth MOS transistor having a gate to which the output of said differential amplifier is applied, and a load connected in series with said fifth MOS transistor, and wherein the output of said amplifier is taken out from between said fifth MOS transistor and said load.

Claim 10

The level conversion input circuit as defined in claim 1 wherein said first MOS transistor comprises a P-type MOSFET, said second MOS transistor comprises an N-type MOSFET, a voltage of an ECL level is applied to the input of said first input circuit and a voltage of a CMOS level is taken out from the output of said first input circuit.

Claim 11

The level conversion input circuit as defined in claim 9 which includes a CMOS inverter connected to the output of said first input circuit.

Claim 12

The level conversion input circuit as defined in claim 1 wherein said first input circuit includes a third MOS transistor which has a channel of the same conductivity type as said second MOS transistor and which has a first terminal, a second terminal and a gate terminal, wherein said second terminal of said third MOS transistor is coupled to the second terminal of said first MOS transistor, said first terminal of said third MOS transistor is coupled to second terminal of said second MOS transistor, and said gate terminal of said third MOS transistor is coupled to the input of said first input circuit.

Claim 13

The level conversion input circuit as defined in claim 11 wherein said first MOS transistor comprises a P-type MOSFET, said second and third MOS transistors are comprised of N-type MOSFETs, respectively, a voltage of an ECL level is applied to the input of said first input circuit and a voltage of a CMOS level is taken out from the output of said first input circuit.

Claim 14

The level conversion input circuit as defined in claim 12 which includes a CMOS inverter connected to the output of said first input circuit.

Claim 15

A CMOS integrated circuit equipped with a level conversion input circuit comprising: a pluarlity of first input circuits connected in parallel with one another between a first voltage source and a second voltage source, each including at least a P-type first MOS transistor and an N-type second MOS transistor connected in series with one another between said first and second voltage sources, the gate of said first MOS transistor being connected to the input of said input circuit receiving an input signal, the output of said input circuit being taken out from between said first and second MOS transistors; a plurality of CMOS inverters, wherein said CMOS inverters are respectively arranged so that one CMOS inverter is coupled to the output of one input circuit; and a voltage generation circuit applying a voltage to the gate of said second MOS transistor of each of said first input circuits to control the logic threshold voltage of said first input circuits, wherein the output of one of said CMOS inverters is used to drive an internal circuit of said integrated circuit.

Claim 16

A CMOS integrated circuit equipped with a level conversion input circuit comprising: a pluarlity of first input circuits connected in parallel with one another between a first voltage source and a second voltage source, each including at least a P-type first MOS transistor and an N-type second MOS transistor connected in series with one another between said first and second voltage sources, the gate of said first MOS transistor being connected to the input of said input circuit receiving an input signal, the output of said input circuit being taken out from between said first and second MOS transistors; a plurality of CMOS inverters, wherein said CMOS inverters are respectively arranged so that one CMOS inverter is coupled to the output of one input circuit; and a voltage generation circuit applying a voltage to the gate of said second MOS transistor of each of said first input circuits to control the logic threshold voltage of said first input circuits, wherein the output of one of said CMOS inverters is used to drive an internal circuit of said integrated circuit.

Claim 17

The CMOS integrated circuit equipped with a level conversion input circuit as defined in claim 14 wherein each of said first input circuits and each of said CMOS inverters are disposed in the periphery of an area where said internal circuit is disposed in said integrated circuit.