High density gallium arsenide source driven logic circuit

Claim 2

A high density GaAs source driven logic circuit comprising: input switch transistor means having source, drain and gate electrodes, at least one non-inverting input line coupled to said source electrode, at least one inverting input line coupled to said gate electrode, an output line coupled to said drain electrode, current source pull-down transistor means coupled to said output line, and current source pull-down transistor means coupled to said gate electrode of said input switch transistor means, whereby said at least one inverting input signal on one of said inverting input lines is logically combined by said input switch transistor means with a non-inverting input signal on said non-inverting input line to provide a logic function output on said output line.

Claim 3

A high density GaAs source driven logic circuit as set forth in claim one which further includes a level shifting network, and wherein said at least one inverting input line comprises a plurality of input lines and each having a said inverting input signal thereon which is level shifted by said level shifting network.

Claim 4

A high density GaAs source driven logic circuit as set forth in claim 2 wherein the logic function output on said output line is an OR function of the inverting and non-inverting input lines, said level shifting network being coupled in series with said inverting inputs coupled to said gate electrode of said input switch transistor means to provide inverting logic inputs, a power source, said current source pull-down transistor means being further coupled between said gate electrode of said input switch transistor means and said power source, said current source pull-up transistor means being further coupled to said drain electrode of said input switch transistor means, and said output line being coupled to said source of said current source pull-up transistor means, whereby one of said plurality of said input lines is applied directly to said input switching transistor means and said plurality of inverting input lines are applied to said level shifting network before being applied to the gate electrode of said input switch transistor means to provide a logic function output on said output line having input voltage inversion.

Claim 5

A high density GaAs source driven logic circuit as set forth in claim 1 wherein said at least one inverting input line comprises at least a pair of inverting input lines, said at least one non-inverting input line comprises at least a pair of non-inverting input lines, said current source pull-down transistor means comprises at least a pair of transistors, and said logic function output on said output line comprises an EXCLUSIVE NOR output.

Claim 6

A high density GaAs source driven logic circuit as set forth in claim 1 wherein the input signals on said non-inverting and said inverting input lines comprises two predetermined logic voltage levels on said input lines and said input switch transistor means provides said predetermined voltage logic levels on said output line.

Claim 7

A high density GaAs source driven logic circuit as set forth in claim 5 wherein said input signals are logically combined in said input switch transistor means to provide a non-inverting logic function output on said output line having the same logic levels as said input signals.

Claim 8

A high density GaAs source driven logic circuit comprising: a pair of input switch transistors having source, drain and gate electrodes, a pair of logic inputs, one of said pair of said logic inputs being coupled to said source electrode of one of said pair of input switch transistors and to the gate electrode of the other input switch transistor, the other one of pair of said logic inputs being coupled to said gate electrode of said one of said pair of input switch transistors and to the source electrode of said other input switch transistor, a level shifting network respectively coupled in series with each one of said pair of said logic inputs that is coupled to said gate electrodes of said pair of input switch transistors, a power source, a pair of current source pull-down transistors coupled between said gate electrodes of said input switch transistors and said power source, a current source pull-up transistor having a source electrode coupled to said drain electrodes of said input switch transistors, and an output line coupled to said source electrode of said current source pull-up transistor, whereby an exclusive NOR logic function output is provided on said output line.

Claim 9

A high density GaAs source driven logic circuit comprising: a pair of input switch transistors having source, drain and gate electrodes, a pair of logic inputs, one of said pair of said logic inputs being coupled to said source electrode of one of said pair of input switch transistors and to the gate electrode of the other input switch transistor, the other one of pair of said logic inputs being coupled to said gate electrode of said one of said pair of input switch transistors and to the source electrode of said other input switch transistor, a level shifting network respectively coupled in series with each one of said pair of said logic inputs that is coupled to said gate electrodes of said pair of input switch transistors, a power source, a pair of current source pull-down transistors coupled between said gate electrodes of said input switch transistors and said power source, a current source pull-up transistor having a source electrode coupled to said drain electrodes of said input switch transistors, and an output line coupled to said source electrode of said current source pull-up transistor, whereby an exclusive NOR logic function output is provided on said output line.