US4469962A — High-speed MESFET circuits using depletion mode M…

Claim 1

Independent Claim 182 words

An electronic circuit biased about a reference voltage and comprising: (a) a logic element responsive to a data input signal including a high logic level of a first voltage and a low logic level of a second voltage; (b) a clock means for supplying an oscillating electric potential clock waveform having a minimum and a maximum voltage with respect to the reference voltage, wherein: (i) the absolute value of the clock waveform's minimum voltage is greater than the absolute value of the clock waveform's maximum voltage, and (ii) the clock waveform's maximum voltage is approximately equal to or more negative than both the first and second voltages of the logic element; and (c) a metal-semiconductor field-effect transistor (MESFET) switch whose source-to-drain impedance is controlled by the voltage level of the clock waveform applied at its gate electrode and having its source connected to the input of the logic element and its drain receiving the data input signal, and wherein the switch MESFET's pinch-off voltage is more positive than the clock waveform's minimum voltage and more negative than the clock waveform's maximum voltage.

Claim 2

Dependent Claim 182 words

An electronic circuit biased about a reference voltage and comprising: (a) a logic element responsive to a data input signal including a high logic level of a first voltage and a low logic level of a second voltage; (b) a clock means for supplying an oscillating electric potential clock waveform having a minimum and a maximum voltage with respect to the reference voltage, wherein: (i) the absolute value of the clock waveform's minimum voltage is greater than the absolute value of the clock waveform's maximum voltage, and (ii) the clock waveform's maximum voltage is approximately equal to or more negative than both the first and second voltages of the logic element; and (c) a metal-semiconductor field-effect transistor (MESFET) switch whose source-to-drain impedance is controlled by the voltage level of the clock waveform applied at its gate electrode and having its source connected to the input of the logic element and its drain receiving the data input signal, and wherein the switch MESFET's pinch-off voltage is more positive than the clock waveform's minimum voltage and more negative than the clock waveform's maximum voltage.

Claim 3

Dependent Claim 25 words

The electronic circuit of claim 1 wherein the MESFET switch is a gallium arsenide MESFET and the electronic circuit is realized as an integrated circuit.

Claim 4

Dependent Claim 25 words

The electronic circuit of claim 1 wherein the clock means generates an oscillating electric potential clock waveform generally in the form of a square wave.

Claim 5

Dependent Claim 26 words

The electronic circuit of claim 3 wherein the clock means connected to the gate of the MESFET switch periodically turns the MESFET switch on and off.

Claim 6

Dependent Claim 45 words

The electronic circuit of claim 4 wherein the clock means oscillates between -1 and -3 volts, wherein the high logic level is 0 volts and the low logic level is -1 volt, and wherein the pinch-off voltage of the MESFET switch is approximately -2 volts.

Claim 7

Dependent Claim 149 words

The electronic circuit of claims 2, 3, 4, or 5 wherein the logic element comprises: (a) a first MESFET having its drain connected to a source of electric potential and its source electrode connected to its gate; (b) a second MESFET having its drain connected to the source electrode of the first MESFET, and its source electrode connected to ground; (c) a third MESFET having its gate and its source electrode connected to a source of electric potential having a negative polarity; and (d) plural diodes connected in series, with the anode of the first diode connected to the drain of the second MESFET and the cathode of the last diode connected to the drain of the third MESFET; wherein the gate of the second MESFET is the input electrode of the logic element and the drain of the third MESFET is the output electrode of the logic element.

Claim 8

Dependent Claim 87 words

The electronic circuit of claims 1 or 5 further comprising an identical second electronic circuit wherein the output of the logic element of the first electronic circuit is connected to the drain electrode of the MESFET switch of the second electronic circuit, and wherein the drain-to-source impedance of the MESFET switch of the second electronic circuit is varied at the same frequency as that of the first electronic circuit by a periodic clock signal applied at its gate electrode which is 180 degrees out of phase therewith.

Claim 9

Dependent Claim 154 words

A circuit comprising: (a) a logic element responsive to data of first and second negative voltage potentials, said logic element having a depletion mode MESFET data input gate; and (b) a depletion mode MESFET transmission gate operatively associated with said data input gate for enabling the selective serial transmission of data therethrough to said logic element in response to clock signals of third and fourth negative voltage potentials, the pinch-off threshold voltage potential of said data input gate being between approximately said first and second negative voltage potentials, the pinch-off threshold voltage potential of said transmission gate being between approximately said third and fourth negative voltage potentials, said third negative voltage potential being approximately equal to or more negative than said second negative voltage potential, said first negative voltage potential being more positive than said second negative voltage potential, and said fourth negative voltage potential being more negative than said third negative voltage potential.

Claim 10

Dependent Claim 154 words

A circuit comprising: (a) a logic element responsive to data of first and second negative voltage potentials, said logic element having a depletion mode MESFET data input gate; and (b) a depletion mode MESFET transmission gate operatively associated with said data input gate for enabling the selective serial transmission of data therethrough to said logic element in response to clock signals of third and fourth negative voltage potentials, the pinch-off threshold voltage potential of said data input gate being between approximately said first and second negative voltage potentials, the pinch-off threshold voltage potential of said transmission gate being between approximately said third and fourth negative voltage potentials, said third negative voltage potential being approximately equal to or more negative than said second negative voltage potential, said first negative voltage potential being more positive than said second negative voltage potential, and said fourth negative voltage potential being more negative than said third negative voltage potential.

Claim 11

Dependent Claim 14 words

The circuit of claim 8 further characterized as being fabricated on a monolithic substrate.

Claim 12

Dependent Claim 35 words

The circuit of claim 9 wherein said first and second negative voltage potentials range from approximately 0 to -1 volts and said second and third negative voltage potentials range from approximately -1 to -3 volts.

Claim 13

Dependent Claim 20 words

The circuit of claim 8 wherein said MESFET data input gate and said MESFET transmission gate are both GaAs devices.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1987-09-04	1988-03-05	1988-09-04	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1991-09-04	1992-03-05	1992-09-04	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1995-09-04	1996-03-05	1996-09-04	$7700.00	Window Closed / Lapsed

High-speed MESFET circuits using depletion mode MESFET signal transmission gates

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