US4404480A
Expired / Lapsed
US
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High speed-low power gallium arsenide basic logic circuit
Assignee: Unisys Corp
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Filing: 1982-02-01
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Granted: 1983-09-13
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Expires: 2002-02-01
Abstract
Abstract The present invention provides a high-speed low-power gallium arsenide basic logic circuit which is capable of being driven by either emitter coupled logic or gallium arsenide logic level signals to provide combinational logic gating such as OR-AND, OR-NAND, OR-AND-OR and OR-AND-NOR capable of driving directly either emitter coupled logic or gallium arsenide logic circuits. The combinational logic gating is basically accomplished by diode logic which performs other functions and which requires less area on an integrated circuit chip than active switching transistors.
Inventors
- 👤 Stephen A. Ransom
- 👤 Tedd K. Stickel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:18
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018535; H03K19/02; H03K19/08; H03K19/094; H03K19/0956
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
238 words
A high speed gallium arsenide basic logic circuit for processing either emitter coupled logic (ECL) or gallium arsenide (GaAs) signals comprising: a plurality of OR gates each having a plurality of individual input lines with at least one forward biased diode connected in series with each input line, each said OR gate having an output node connected to said input lines at the cathode side of said diodes, said OR gates providing a voltage shift down across said diodes of said input lines, a plurality of level shifting networks, each being connected in series with one of said OR gates, each said level shifting network comprising at least three diodes of which at least two of said diodes are forward biased to provide a further voltage shift down, said plurality of level shifting networks comprising a diode AND gate, each said level shifting network having at least one diode which is connected in series to cause a level shift up, each diode of said AND gate being forward biased by a pull-up transistor connected to the anode side and a pull-down transistor connected to the cathode side, and an amplifier stage connected to the output of said level shifting network, whereby voltage signal levels applied to the input of said OR gates are processed through logic decisions while being shifted down and shifted up before being amplified, thus, providing enhanced speed power products in simplified GaAs logic circuitry.
Claim 2
Dependent Claim
238 words
A high speed gallium arsenide basic logic circuit for processing either emitter coupled logic (ECL) or gallium arsenide (GaAs) signals comprising: a plurality of OR gates each having a plurality of individual input lines with at least one forward biased diode connected in series with each input line, each said OR gate having an output node connected to said input lines at the cathode side of said diodes, said OR gates providing a voltage shift down across said diodes of said input lines, a plurality of level shifting networks, each being connected in series with one of said OR gates, each said level shifting network comprising at least three diodes of which at least two of said diodes are forward biased to provide a further voltage shift down, said plurality of level shifting networks comprising a diode AND gate, each said level shifting network having at least one diode which is connected in series to cause a level shift up, each diode of said AND gate being forward biased by a pull-up transistor connected to the anode side and a pull-down transistor connected to the cathode side, and an amplifier stage connected to the output of said level shifting network, whereby voltage signal levels applied to the input of said OR gates are processed through logic decisions while being shifted down and shifted up before being amplified, thus, providing enhanced speed power products in simplified GaAs logic circuitry.
Claim 3
Dependent Claim
41 words
A high speed GaAs basic logic circuit as set forth in claim 1, wherein said amplifier comprises a GaAs common source transistor amplifier for producing output signals capable of driving GaAs logic from GaAs logic signals applied to said input lines.
Claim 4
Dependent Claim
32 words
A high speed GaAs basic logic circuit as set forth in claim 2, wherein said common source transistor amplifier comprises a GaAs pull-up transistor and a GaAs pull-down transistor connected in series.
Claim 5
Dependent Claim
64 words
A high speed GaAs basic logic circuit as set forth in claim 1, wherein said amplifier comprises a GaAs differential amplifier of the type having an input branch and an output branch, and an output line connected to one of said branches for producing output signals capable of driving GaAs logic from either GaAs or ECL logic voltage level signals at said input lines.
Claim 6
Dependent Claim
71 words
A high speed GaAs basic logic circuit as set forth in claim 1, wherein said amplifier comprises a GaAs differential amplifier of the type having an input branch and an output branch, and a GaAs source follower transistor output stage connected to said output branch of said differential amplifier for producing output signals capable of driving ECL logic from either GaAs or ECL logic voltage level signals at said input lines.
Claim 7
Dependent Claim
52 words
A high speed GaAs basic logic circuit as set forth in claim 1, wherein said level shifting networks each include at least four GaAs diodes of which three of said diodes shift the voltage level at said input lines down and at least one of said diodes shifts the voltage level up.
Claim 8
Dependent Claim
32 words
A high speed GaAs basic logic circuit as set forth in claim 6, wherein said GaAs diode which shifts the input line voltage level up also performs an AND gate logic function.
Claim 9
Dependent Claim
59 words
A high speed GaAs basic logic circuit as set forth in claim 1, which further includes a second set of OR gates connected to a second plurality of level shifting networks which form a second AND gate, the outputs of said level shifting networks being connected to an output OR gate intermediate said level shifting networks and said amplifier.
Claim 10
Dependent Claim
43 words
A high speed GaAs basic logic circuit as set forth in claim 8, which further includes individual input signal lines, and said output OR gate being characterized by receiving the outputs of said AND gates as well as the individual input signal lines.
Claim 11
Dependent Claim
40 words
A high speed GaAs basic logic circuit as set forth in claim 9, wherein said amplifier is a differential amplifier for producing output signals capable of driving GaAs logic from either GaAs or ECL voltage signals at said input lines.
References Cited (Backward Citations)
US3299363A
Cited
US4300064A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-12 | 1987-03-14 | 1987-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-12 | 1991-03-14 | 1991-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-12 | 1995-03-14 | 1995-09-13 | $7700.00 | Window Closed / Lapsed |