§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
US4471238A Expired / Lapsed US ⏱️ 0.0 years remaining

Current-driven logic circuits

Assignee: The AT&T MVPD Group LLC
•
Filing: 1982-06-01
•
Granted: 1984-09-11
•
Expires: 2002-06-01
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An enhancement-mode field effect transistor (ENFET) logic circuit providing greater fan-out capability. The logic circuit employs a conventional common-source inverter section, but additionally incorporates a current-driving section which drives the common-source inverter section. A current-driven inverter logic circuit is realized by employing a second ENFET transistor to drive the gate of the common-source inverter section. A current-driven NOR gate is realized by employing two ENFET transistors in parallel which drive the common-source inverter section. Also a current-driven NAND gate is realized by utilizing a single transistor having two gate inputs to drive the common-source inverter section. The use of sweep-out circuitry allows for control of the operational speed of the device. The logic circuit designs have high fan-out capability compared to the common-source inverter circuit alone.

Inventors

  • 👤 Ronald M. Hickling
  • 👤 Jay E. Landenberger

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 20:15
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/0952

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 138 words
A logic circuit comprising: a common source inverter section including a first enhancement mode field effect transistor (ENFET) having gate, source and drain electrodes, said drain electrode being connected to a signal output terminal, said signal output terminal being coupled to a first power source terminal through a load means, said source electrode being connected to a second power source terminal; a current driving section including a second ENFET having gate, source and drain electrodes, said second ENFET gate electrode being coupled to a first signal input terminal, said second ENFET drain electrode being connected to said frist power source terminal, said second ENFET source electrode being connected to said first ENFET gate electrode, and a current source being coupled between said first ENFET gate electrode and said second power source terminal for effecting a constant current therebetween.
Claim 2
Dependent Claim 138 words
A logic circuit comprising: a common source inverter section including a first enhancement mode field effect transistor (ENFET) having gate, source and drain electrodes, said drain electrode being connected to a signal output terminal, said signal output terminal being coupled to a first power source terminal through a load means, said source electrode being connected to a second power source terminal; a current driving section including a second ENFET having gate, source and drain electrodes, said second ENFET gate electrode being coupled to a first signal input terminal, said second ENFET drain electrode being connected to said frist power source terminal, said second ENFET source electrode being connected to said first ENFET gate electrode, and a current source being coupled between said first ENFET gate electrode and said second power source terminal for effecting a constant current therebetween.
Claim 3
Dependent Claim 16 words
The logic circuit of claim 1 further characterized in that it is a current-driven inverter circuit.
Claim 4
Dependent Claim 68 words
The logic circuit of claim 1 further comprising a third ENFET having gate, source and drain electrodes, said third ENFET gate electrode being coupled to a second signal input terminal, said third ENFET drain electrode being connected to said first power source terminal, and said third ENFET source electrode being connected to said first ENFET gate electrode so that said logic circuit is a current-driven NOR gate circuit.
Claim 5
Dependent Claim 35 words
The logic circuit of claim 1 further characterized in that said second ENFET has a second gate electrode coupled to a second signal input terminal so that said logic circuit is a current-driven NAND gate.

References Cited (Backward Citations)

US4093925A Cited
US4300064A Cited
US4394589A Cited
JPS5726471A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-09-11 1988-03-12 1988-09-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-09-11 1992-03-12 1992-09-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-09-11 1996-03-12 1996-09-11 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag