US4438351A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gallium arsenide MIS integrated circuits
Assignee: Individual
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Filing: 1981-06-09
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Granted: 1984-03-20
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Expires: 2001-06-09
Abstract
Abstract A technique to utilize GaAs insulated gate field effect transistors (IGFETs) with large surface state densities in digital integrated circuits including latches is described. In this technique, the threshold voltage is electrically set to obtain enhancement mode characteristics of the IGFETs. Due to changes in surface charge with time, these circuits will not function at very low frequencies, but are very useful at gigahertz frequencies.
Inventors
- 👤 Fritz L. Schuermeyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:11
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356069; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0952; H03K3/3562
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
241 words
An integrated circuit using metal insulator semiconductor field effect transistors (MISFET) of the buried channel type in which the semiconductor comprises an active layer of gallium arsenide (GaAs), each transistor having a source, a drain, and at least one gate, with a gate insulator of a material which provides large interface trap states, the region of the active layer under the gate having a doping and being of sufficient thickness so that when there is a direct connection between the source and gate providing zero direct-current bias a depletion layer extends only partly through said region and the transistor is therefore conducting, said integrated circuit comprising: at least one inverter circuit with load means and an active transistor in series across a direct current bias supply with a node between them, the drain and source of the active transistor being coupled to said node and to a terminal of said bias supply respectively, an input connection to the gate of the active transistor, means to electrically set a threshold voltage for bias at the gate of the active transistor via said interface trap states, and to maintain said threshold voltage by signals above a cutoff frequency at said input connection which may vary between a given high level substantially equal to the bias potential at said source such that an initial high-level signal charges said interface trap states and the internal between high-level signals is sufficiently short to maintain the charge.
Claim 2
Dependent Claim
241 words
An integrated circuit using metal insulator semiconductor field effect transistors (MISFET) of the buried channel type in which the semiconductor comprises an active layer of gallium arsenide (GaAs), each transistor having a source, a drain, and at least one gate, with a gate insulator of a material which provides large interface trap states, the region of the active layer under the gate having a doping and being of sufficient thickness so that when there is a direct connection between the source and gate providing zero direct-current bias a depletion layer extends only partly through said region and the transistor is therefore conducting, said integrated circuit comprising: at least one inverter circuit with load means and an active transistor in series across a direct current bias supply with a node between them, the drain and source of the active transistor being coupled to said node and to a terminal of said bias supply respectively, an input connection to the gate of the active transistor, means to electrically set a threshold voltage for bias at the gate of the active transistor via said interface trap states, and to maintain said threshold voltage by signals above a cutoff frequency at said input connection which may vary between a given high level substantially equal to the bias potential at said source such that an initial high-level signal charges said interface trap states and the internal between high-level signals is sufficiently short to maintain the charge.
Claim 3
Dependent Claim
213 words
An integrated circuit using metal insulator semiconductor field effect transistors (MISFET) of the buried channel type having large interface trap states in which the semiconductor is qallium arsenide (GaAs), each transistor having a source, a drain, and at least one gate, said integrated circuit comprising: two inverter circuits, each inverter circuit having load means and an active transistor in series across a direct current bias supply with a node between them, the drain and source of the active transistor being coupled to said node and to a terminal of said bias supply respectively, an input connection to the gate of the active transistor, means to electrically set a threshold voltage for bias at the gate of the active transistor via said interface trap states, and to maintain said threshold voltage by signals above a cutoff frequency at said input connection which vary between a given high level substantially equal to the bias potential at said source such that an initial high-level signal charges said interface trap states and that interval between high-level signals is sufficiently short to maintain the charge: wherein said inverter circuits are connected as two branches of a latch, with direct cross coupling from said node of each branch to the gate of the active transistor of the other branch.
Claim 4
Dependent Claim
213 words
An integrated circuit using metal insulator semiconductor field effect transistors (MISFET) of the buried channel type having large interface trap states in which the semiconductor is qallium arsenide (GaAs), each transistor having a source, a drain, and at least one gate, said integrated circuit comprising: two inverter circuits, each inverter circuit having load means and an active transistor in series across a direct current bias supply with a node between them, the drain and source of the active transistor being coupled to said node and to a terminal of said bias supply respectively, an input connection to the gate of the active transistor, means to electrically set a threshold voltage for bias at the gate of the active transistor via said interface trap states, and to maintain said threshold voltage by signals above a cutoff frequency at said input connection which vary between a given high level substantially equal to the bias potential at said source such that an initial high-level signal charges said interface trap states and that interval between high-level signals is sufficiently short to maintain the charge: wherein said inverter circuits are connected as two branches of a latch, with direct cross coupling from said node of each branch to the gate of the active transistor of the other branch.
Claim 5
Dependent Claim
63 words
An integrated circuit as set forth in claim 2, wherein each branch includes an initiation transistor, said coupling of the drain of the active transistor to said node being via the source-drain path of the initiation transistor, and wherein the circuit is activated by a negative pulse going from high level to low applied to the gates of both of the initiation transistors..
Claim 6
Dependent Claim
39 words
An integrated circuit as set forth in claim 1, 2 or 3, wherein said load means is load transistor having its source and gate connected to said anode, and its drain connected to another terminal of said bias supply.
Claim 7
Independent Claim
225 words
The method of operating an integrated circuit using metal insulator semiconductor field effect transistors (MISFET) of the buried channel type in which the semiconductor comprises an active layer of gallium arsenide (GaAs), with a gate insulator of a material which provides large interface trap states, the region of the active layer under the gate having a doping and being of sufficient thickness so that when there is a direct connection between the source and gate providing zero direct-current bias a depletion layer extends only partly through said region and the transistor is therefore conducting, said integrated circuit comprising at least one inverter circuit with load means and an active transistor in series across a direct current bias supply, with a node between them, the drain and source of the active transistor being coupled to said node and to a terminal of said bias supply respectively, and an input connection to the gate of the active transistor, the method comprising: applying signals at said connection to electrically set a threshold voltage for bias at the gate of the active transistor via said interface trap states, and to maintain said threshold voltage by signals above a cutoff frequency which vary between a given high level and a low level substantially equal to the bias potential at said source such that said interface trap states do not discharge.
Claim 8
Independent Claim
225 words
The method of operating an integrated circuit using metal insulator semiconductor field effect transistors (MISFET) of the buried channel type in which the semiconductor comprises an active layer of gallium arsenide (GaAs), with a gate insulator of a material which provides large interface trap states, the region of the active layer under the gate having a doping and being of sufficient thickness so that when there is a direct connection between the source and gate providing zero direct-current bias a depletion layer extends only partly through said region and the transistor is therefore conducting, said integrated circuit comprising at least one inverter circuit with load means and an active transistor in series across a direct current bias supply, with a node between them, the drain and source of the active transistor being coupled to said node and to a terminal of said bias supply respectively, and an input connection to the gate of the active transistor, the method comprising: applying signals at said connection to electrically set a threshold voltage for bias at the gate of the active transistor via said interface trap states, and to maintain said threshold voltage by signals above a cutoff frequency which vary between a given high level and a low level substantially equal to the bias potential at said source such that said interface trap states do not discharge.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-20 | 1987-09-19 | 1988-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-20 | 1991-09-19 | 1992-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-20 | 1995-09-19 | 1996-03-20 | $7700.00 | Window Closed / Lapsed |