US7058862B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Selecting different 1149.1 TAP domains from update-IR state
Assignee: Texas Instruments Inc
•
Filing: 2001-05-24
•
Granted: 2006-06-06
•
Expires: 2021-05-24
Abstract
Abstract IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
Inventors
- 👤 Lee D. Whetsel
- 👤 Baher S. Haroun
- 👤 Brian J. Lasher
- 👤 Anjali Kinra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:50
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3177; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318555; G01R31/31727
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
70 words
A process of selecting different 1149.1 TAP domain arrangements within an integrated circuit comprising: A. performing an 1149.1 instruction shift operation through a first 1149.1 TAP domain arrangement; B. performing an 1149.1 instruction update operation at the end of the 1149.1 instruction shift operation; and C. in response to said 1149.1 instruction update operation, selecting a second 1149.1 TAP domain arrangement that differs from the first 1149.1 TAP domain arrangement.
Claim 2
Dependent Claim
70 words
A process of selecting different 1149.1 TAP domain arrangements within an integrated circuit comprising: A. performing an 1149.1 instruction shift operation through a first 1149.1 TAP domain arrangement; B. performing an 1149.1 instruction update operation at the end of the 1149.1 instruction shift operation; and C. in response to said 1149.1 instruction update operation, selecting a second 1149.1 TAP domain arrangement that differs from the first 1149.1 TAP domain arrangement.
Claim 3
Dependent Claim
26 words
The process of claim 1 including performing the 1149.1 instruction shift operation in accordance with the 1149.1 IEEE Standard titled Test Access Port and Boundary-Scan Architecture.
Claim 4
Dependent Claim
26 words
The process of claim 1 including performing the 1149.1 instruction update operation in accordance with the 1149.1 IEEE Standard titled Test Access Port and Boundary-Scan Architecture.
Claim 5
Dependent Claim
26 words
The process of claim 1 including performing a select DR operation, a select IR operation, and a capture IR operation before performing the instruction shift operation.
Claim 6
Dependent Claim
24 words
The process of claim 1 including performing one of a select DR operation and a Run Test/Idle operation after performing the instruction update operation.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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