US6570813B2
Expired / Lapsed
US
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Synchronous mirror delay with reduced delay line taps
Assignee: Micron Technology Inc
•
Filing: 2001-05-25
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Granted: 2003-05-27
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Expires: 2021-05-25
Abstract
Abstract A synchronous mirror delay (SMD) clock recovery and skew adjustment circuit for an integrated circuit is described, having a reduced circuit implementation. The SMD clock recovery and skew adjustment circuit incorporates a delay segment into the forward delay line (FDL) and backward delay line (BDL) that accounts for all or some of the non-variable portion of the asserted clock signal time period. This delay segment allows reduction of the FDL and BDL lines to only those portions necessary to sense and adjust for the portion of the asserted clock signal time period that is variable and that must be adjusted for. The invention allows SMD clock recovery and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size.
Inventors
- 👤 Scott Van De Graaff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:23
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G11C7/1072; G11C7/22; G11C7/222
Claims Analysis
Total Claims: 70
Claim 1
Independent Claim
67 words
An SMD circuit comprising: a clock source; a delay segment coupled to the clock source; a data path model coupled to the delay segment; a forward delay line coupled to the data path model; an SMD control circuit coupled to the forward delay line and coupled to the clock source; and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
Claim 2
Dependent Claim
67 words
An SMD circuit comprising: a clock source; a delay segment coupled to the clock source; a data path model coupled to the delay segment; a forward delay line coupled to the data path model; an SMD control circuit coupled to the forward delay line and coupled to the clock source; and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
Claim 3
Dependent Claim
27 words
The SMD circuit of claim 1 , wherein the delay segment has a time delay that is a portion of a time period of the clock source.
Claim 4
Dependent Claim
26 words
The SMD circuit of claim 1 , wherein the delay segment has a time delay that is greater than a time period of the clock source.
Claim 5
Dependent Claim
19 words
The SMD circuit of claim 1 , wherein the delay segment further comprises at least one unit delay element.
Claim 6
Dependent Claim
21 words
The SMD circuit of claim 4 , wherein the at least one unit delay element further comprises a RC delay element.
Claim 7
Dependent Claim
22 words
The SMD circuit of claim 4 , wherein the at least one unit delay element further comprises a skew limited delay element.
Claim 8
Dependent Claim
24 words
The SMD circuit of claim 1 , wherein the forward delay line and the backward delay line further comprises at least one delay element.
Claim 9
Dependent Claim
20 words
The SMD circuit of claim 7 , wherein the delay element further comprises a NAND gate coupled to an inverter.
Claim 10
Dependent Claim
23 words
The SMD circuit of claim 7 , wherein the delay element further comprises a first NAND gate coupled to a second NAND gate.
Claim 11
Dependent Claim
73 words
The SMD circuit of claim 1 , wherein the SMD control circuit further comprises at least one NAND gate, wherein an input of the NAND gate is coupled to a control line, another input of the NAND gate is coupled to an output of a delay element of the forward delay line, and an output of the NAND gate is coupled to an input of a delay element of the backward delay line.
Claim 12
Dependent Claim
69 words
The SMD circuit of claim 1 , wherein the SMD control circuit further comprises at least one latch, wherein an input of the latch is coupled to a control line, another input of the latch is coupled to an output of a delay element of the forward delay line, and an output of the latch is coupled to an input of a delay element of the backward delay line.
Claim 13
Dependent Claim
17 words
The SMD circuit of claim 1 , wherein the SMD circuit is implemented in an integrated circuit.
Claim 14
Dependent Claim
16 words
The SMD circuit of claim 1 , wherein the SMD circuit is implemented in an ASIC.
Claim 15
Dependent Claim
17 words
The SMD circuit of claim 1 , wherein the SMD circuit is implemented in a memory device.
Claim 16
Dependent Claim
16 words
The SMD circuit of claim 14 , wherein the memory device is a DDR memory device.
Claim 17
Dependent Claim
18 words
The SMD circuit of claim 1 , wherein the SMD circuit is implemented in a nonvolatile memory device.
Claim 18
Dependent Claim
79 words
An integrated circuit comprising: a clock input buffer coupled to receive a clock signal with a time period; a delay segment coupled to the clock input buffer; a data path model coupled to the delay segment; a forward delay line coupled to the data path model; an SMD control circuit coupled to the forward delay line and to the clock input buffer; and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
Claim 19
Dependent Claim
79 words
An integrated circuit comprising: a clock input buffer coupled to receive a clock signal with a time period; a delay segment coupled to the clock input buffer; a data path model coupled to the delay segment; a forward delay line coupled to the data path model; an SMD control circuit coupled to the forward delay line and to the clock input buffer; and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
Claim 20
Dependent Claim
27 words
The integrated circuit of claim 17 , wherein the delay segment has a time delay that is a sub-part of the time period of the clock signal.
Claim 21
Dependent Claim
26 words
The integrated circuit of claim 17 , wherein the delay segment has a time delay that is greater than the time period of the clock signal.
Claim 22
Dependent Claim
18 words
The integrated circuit of claim 17 , wherein the delay segment further comprises at least one delay element.
Claim 23
Dependent Claim
20 words
The integrated circuit of claim 20 , wherein the at least one delay element further comprises a RC delay element.
Claim 24
Dependent Claim
21 words
The integrated circuit of claim 20 , wherein the at least one delay element further comprises a skew limited delay element.
Claim 25
Dependent Claim
24 words
The integrated circuit of claim 17 , wherein the forward delay line and the backward delay line further comprises at least one delay element.
Claim 26
Dependent Claim
20 words
The integrated circuit of claim 23 , wherein the delay element further comprises a NAND gate coupled to an inverter.
Claim 27
Dependent Claim
23 words
The integrated circuit of claim 23 , wherein the delay element further comprises a first NAND gate coupled to a second NAND gate.
Claim 28
Dependent Claim
74 words
The integrated circuit of claim 17 , wherein the SMD control circuit further comprises at least one NAND gate, wherein an input of the NAND gate is coupled to the clock input buffer, another input of the NAND gate is coupled to an output of a delay element of the forward delay line, and an output of the NAND gate is coupled to an input of a delay element of the backward delay line.
Claim 29
Dependent Claim
71 words
The integrated circuit of claim 17 , wherein the SMD control circuit further comprises at least one latch, wherein a clock input of the latch is coupled to the clock input buffer, an input of the latch is coupled to an output of a delay element of the forward delay line, and an output of the latch is coupled to an input of a delay element of the backward delay line.
Claim 30
Dependent Claim
86 words
A memory device comprising: an address interface; a data interface; a control interface; and an SMD clock recovery and skew adjustment circuit comprising, a clock source, a delay segment coupled to the clock source, a data path model coupled to the delay segment, a forward delay line coupled to the data path model, an SMD control circuit coupled to the forward delay line and coupled to the clock source, and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
Claim 31
Dependent Claim
86 words
A memory device comprising: an address interface; a data interface; a control interface; and an SMD clock recovery and skew adjustment circuit comprising, a clock source, a delay segment coupled to the clock source, a data path model coupled to the delay segment, a forward delay line coupled to the data path model, an SMD control circuit coupled to the forward delay line and coupled to the clock source, and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
Claim 32
Dependent Claim
14 words
The memory device of claim 28 , wherein the memory device comprises nonvolatile memory.
Claim 33
Dependent Claim
14 words
The memory device of claim 28 , wherein the memory device comprises synchronous memory.
Claim 34
Dependent Claim
14 words
The memory device of claim 30 , wherein the memory device comprises SDRAM memory.
Claim 35
Dependent Claim
14 words
The memory device of claim 30 , wherein the memory device comprises DDR memory.
Claim 36
Dependent Claim
26 words
The memory device of claim 28 , wherein the data interface further comprises a data latch coupled to the SMD clock recovery and skew adjustment circuit.
Claim 37
Dependent Claim
27 words
The memory device of claim 28 , wherein the data interface further comprises a DQS strobe circuit coupled to the SMD clock recovery and skew adjustment circuit.
Claim 38
Dependent Claim
114 words
A DDR memory device interface circuit comprising: a data interface; a DQS signal interface; a data latch coupled to the data interface; and an SMD clock recovery and skew adjustment circuit coupled to the data latch and the DQS signal interface, wherein the SMD clock recovery and skew adjustment circuit comprises, a clock source, a delay segment coupled to the clock source, a data path model coupled to the delay segment, a forward delay line coupled to the data path model, an SMD control circuit coupled to the forward delay line and coupled to the clock source, and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
Claim 39
Dependent Claim
114 words
A DDR memory device interface circuit comprising: a data interface; a DQS signal interface; a data latch coupled to the data interface; and an SMD clock recovery and skew adjustment circuit coupled to the data latch and the DQS signal interface, wherein the SMD clock recovery and skew adjustment circuit comprises, a clock source, a delay segment coupled to the clock source, a data path model coupled to the delay segment, a forward delay line coupled to the data path model, an SMD control circuit coupled to the forward delay line and coupled to the clock source, and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
Claim 40
Dependent Claim
22 words
The DDR memory device interface circuit of claim 35 , wherein the DDR memory device interface circuit is implemented in an ASIC.
Claim 41
Dependent Claim
23 words
The DDR memory device interface circuit of claim 35 , wherein the DDR memory device interface circuit is implemented in a memory device.
Claim 42
Dependent Claim
19 words
The DDR memory device interface circuit of claim 37 , wherein the memory device is a DDR memory device.
Claim 43
Dependent Claim
24 words
The DDR memory device interface circuit of claim 35 , wherein the DDR memory device interface circuit is implemented in a non-volatile memory device.
Claim 44
Independent Claim
67 words
A method of synchronizing with a clock signal comprising: coupling a delay segment to a clock source; coupling a data path model to the delay segment; coupling a forward delay line to the data path model; coupling an SMD control circuit to the forward delay line and to the clock source; and coupling a backward delay line to the SMD control circuit and to the delay segment.
Claim 45
Independent Claim
67 words
A method of synchronizing with a clock signal comprising: coupling a delay segment to a clock source; coupling a data path model to the delay segment; coupling a forward delay line to the data path model; coupling an SMD control circuit to the forward delay line and to the clock source; and coupling a backward delay line to the SMD control circuit and to the delay segment.
Claim 46
Dependent Claim
26 words
The method of claim 40 , wherein the delay segment has a time delay that is a portion of a time period of the clock source.
Claim 47
Dependent Claim
25 words
The method of claim 40 , wherein the delay segment has a time delay that is greater than a time period of the clock source.
Claim 48
Dependent Claim
19 words
The method of claim 40 , wherein the delay segment further comprises forming at least one unit delay element.
Claim 49
Dependent Claim
22 words
The method of claim 43 , wherein forming the at least one unit delay element further comprises forming a RC delay element.
Claim 50
Dependent Claim
23 words
The method of claim 43 , wherein forming the at least one unit delay element further comprises forming a skew limited delay element.
Claim 51
Dependent Claim
24 words
The method of claim 40 , wherein the forward delay line and the backward delay line further comprises forming at least one delay element.
Claim 52
Dependent Claim
20 words
The method of claim 46 , wherein the delay element further comprises forming a NAND gate coupled to an inverter.
Claim 53
Dependent Claim
23 words
The method of claim 46 , wherein the delay element further comprises forming a first NAND gate coupled to a second NAND gate.
Claim 54
Dependent Claim
73 words
The method of claim 40 , wherein the SMD control circuit further comprises forming at least one NAND gate, wherein an input of the NAND gate is coupled to a control line, another input of the NAND gate is coupled to an output of a delay element of the forward delay line, and an output of the NAND gate is coupled to an input of a delay element of the backward delay line.
Claim 55
Dependent Claim
69 words
The method of claim 40 , wherein the SMD control circuit further comprises forming at least one latch, wherein an input of the latch is coupled to a control line, another input of the latch is coupled to an output of a delay element of the forward delay line, and an output of the latch is coupled to an input of a delay element of the backward delay line.
Claim 56
Dependent Claim
21 words
The method of claim 46 , further comprising minimizing the number of delay elements in the forward and backward delay lines.
Claim 57
Dependent Claim
27 words
The method of claim 46 , further comprising increasing adjustment granularity by decreasing a time delay of the delay elements in the forward and backward delay lines.
Claim 58
Dependent Claim
24 words
The method of claim 40 , further comprising selecting the delay segment to minimize the circuit size of the forward and backward delay lines.
Claim 59
Dependent Claim
25 words
The method of claim 40 , further comprising selecting the delay segment to match a non-variable portion of the time period of the clock source.
Claim 60
Dependent Claim
26 words
The method of claim 54 , further comprising selecting the delay segment to maximize the matched non-variable portion of the time period of the clock source.
Claim 61
Independent Claim
93 words
A method of synchronizing a memory device with a clock signal comprising: forming an address interface; forming a data interface; forming a control interface; and forming an SMD clock recovery and skew adjustment circuit comprising, coupling a delay segment to a clock source, coupling a data path model to the delay segment, coupling a forward delay line to the data path model, coupling an SMD control circuit to the forward delay line and to the clock source, and coupling a backward delay line to the SMD control circuit and to the delay segment.
Claim 62
Independent Claim
93 words
A method of synchronizing a memory device with a clock signal comprising: forming an address interface; forming a data interface; forming a control interface; and forming an SMD clock recovery and skew adjustment circuit comprising, coupling a delay segment to a clock source, coupling a data path model to the delay segment, coupling a forward delay line to the data path model, coupling an SMD control circuit to the forward delay line and to the clock source, and coupling a backward delay line to the SMD control circuit and to the delay segment.
Claim 63
Dependent Claim
13 words
The method of claim 56 , wherein the memory device comprises non-volatile memory.
Claim 64
Dependent Claim
13 words
The method of claim 56 , wherein the memory device comprises synchronous memory.
Claim 65
Dependent Claim
14 words
The memory device of claim 58 , wherein the memory device comprises SDRAM memory.
Claim 66
Dependent Claim
14 words
The memory device of claim 58 , wherein the memory device comprises DDR memory.
Claim 67
Dependent Claim
31 words
The method of claim 56 , wherein forming the data interface further comprises forming a data latch and coupling the data latch to the SMD clock recovery and skew adjustment circuit.
Claim 68
Dependent Claim
30 words
The method of claim 56 , wherein forming the data interface further comprises forming a DQS strobe circuit and coupling it to the SMD clock recovery and skew adjustment circuit.
Claim 69
Independent Claim
125 words
A method for synchronizing a DDR memory device interface circuit with a clock source comprising: forming a data interface; forming a DQS signal interface; forming a data latch coupled to the data interface; and forming an SMD clock recovery and skew adjustment circuit coupled to the data latch and the DQS signal interface, wherein the SMD clock recovery and skew adjustment circuit comprises, a clock source, a delay segment coupled to the clock source, a data path model coupled to the delay segment, a forward delay line coupled to the data path model, an SMD control circuit coupled to the forward delay line and to the clock source, and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
Claim 70
Independent Claim
125 words
A method for synchronizing a DDR memory device interface circuit with a clock source comprising: forming a data interface; forming a DQS signal interface; forming a data latch coupled to the data interface; and forming an SMD clock recovery and skew adjustment circuit coupled to the data latch and the DQS signal interface, wherein the SMD clock recovery and skew adjustment circuit comprises, a clock source, a delay segment coupled to the clock source, a data path model coupled to the delay segment, a forward delay line coupled to the data path model, an SMD control circuit coupled to the forward delay line and to the clock source, and a backward delay line coupled to the SMD control circuit and coupled to the delay segment.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-05-26 | 2006-11-25 | 2007-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-26 | 2010-11-25 | 2011-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-26 | 2014-11-25 | 2015-05-27 | $7700.00 | Window Closed / Lapsed |