US6137325A
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Device and methods in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution
Assignee: Micron Technology Inc
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Filing: 1998-06-22
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Granted: 2000-10-24
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Expires: 2018-06-22
Abstract
Abstract An inventive digital delay locked loop (DLL) for outputting at least first and second output clocks includes delay elements for receiving an input clock and outputting a first series of delayed clocks, each lagging the input clock more than its predecessor. A phase detector compares relative phases of the first output clock and the input clock and outputs count-up or count-down control signals in accordance therewith. First and second counters output respective first and second counts in response to the count-up or count-down control signals, and a first multiplexer selects and outputs the first output clock from among the first series of delayed clocks in accordance with the first count. Also, interpolation circuitry receives a portion of the first series of delayed clocks and outputs same, along with a plurality of interpolated clocks, in the form of a second series of delayed clocks, each lagging the input clock more than its predecessor. A second multiplexer then selects and outputs the second output clock from among the second series of delayed clocks in accordance with the second count. As a result, at least one of the clocks is generated with improved resolution over conventional DLLs.
Inventors
- 👤 James E. Miller, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:14
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; H03K; H03K5/00; H03K5/15; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
140 words
A device for outputting first and second output signals, each lagging an input signal by a controlled amount different than the other, the device comprising: circuitry for receiving the input signal and outputting first and second series of delayed signals, each delayed signal in each series lagging the input signal more than its predecessor in its respective series, the second series including a portion of the first series and a plurality of signals interpolated therefrom; circuitry for comparing relative phases of at least one of the first and second output signals and the input signal and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output signals from among the respective first and second series of delayed signals in response to the control signals.
Claim 2
Independent Claim
140 words
A device for outputting first and second output signals, each lagging an input signal by a controlled amount different than the other, the device comprising: circuitry for receiving the input signal and outputting first and second series of delayed signals, each delayed signal in each series lagging the input signal more than its predecessor in its respective series, the second series including a portion of the first series and a plurality of signals interpolated therefrom; circuitry for comparing relative phases of at least one of the first and second output signals and the input signal and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output signals from among the respective first and second series of delayed signals in response to the control signals.
Claim 3
Dependent Claim
20 words
The device of claim 1, wherein the receiving circuitry comprises a plurality of delay elements and interpolation circuitry coupled thereto.
Claim 4
Dependent Claim
32 words
The device of claim 2, wherein the interpolation circuitry comprises a plurality of buffers, at least two of which have outputs coupled to an input of another of the plurality of buffers.
Claim 5
Dependent Claim
20 words
The device of claim 1, wherein the comparing circuitry comprises a phase detector for outputting count-up and count-down control signals.
Claim 6
Dependent Claim
21 words
The device of claim 1, wherein the selecting circuitry comprises a plurality of counters and a plurality of multiplexers coupled thereto.
Claim 7
Dependent Claim
14 words
The device of claim 1, wherein the device comprises a delay locked loop (DLL).
Claim 8
Dependent Claim
20 words
The device of claim 1, wherein at least one of the first and second output signals comprises a quadrature clock.
Claim 9
Dependent Claim
13 words
The device of claim 1, wherein the input signal comprises an input clock.
Claim 10
Dependent Claim
151 words
A Synchronous Dynamic Random Access Memory (SDRAM) including a delay locked loop (DLL) for outputting first and second output clocks, each lagging an input clock by a controlled amount different than the other, the DLL comprising: circuitry for receiving the input clock and outputting first and second series of delayed clocks, each delayed clock in each series lagging the input clock more than its predecessor in its respective series, the second series including a portion of the first series and a plurality of clocks interpolated therefrom; circuitry for comparing relative phases of at least one of the first and second output clocks and the input clock and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output clocks from among the respective first and second series of delayed clocks in response to the control signals.
Claim 11
Dependent Claim
151 words
A Synchronous Dynamic Random Access Memory (SDRAM) including a delay locked loop (DLL) for outputting first and second output clocks, each lagging an input clock by a controlled amount different than the other, the DLL comprising: circuitry for receiving the input clock and outputting first and second series of delayed clocks, each delayed clock in each series lagging the input clock more than its predecessor in its respective series, the second series including a portion of the first series and a plurality of clocks interpolated therefrom; circuitry for comparing relative phases of at least one of the first and second output clocks and the input clock and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output clocks from among the respective first and second series of delayed clocks in response to the control signals.
Claim 12
Dependent Claim
177 words
An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, processor, and memory devices including a device for outputting first and second output signals, each lagging an input signal by a controlled amount different than the other, the device comprising: circuitry for receiving the input signal and outputting first and second series of delayed signals, each delayed signal in each series lagging the input signal more than its predecessor in its respective series, the second series including a portion of the first series and a plurality of signals interpolated therefrom; circuitry for comparing relative phases of at least one of the first and second output signals and the input signal and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output signals from among the respective first and second series of delayed signals in response to the control signals.
Claim 13
Dependent Claim
177 words
An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, processor, and memory devices including a device for outputting first and second output signals, each lagging an input signal by a controlled amount different than the other, the device comprising: circuitry for receiving the input signal and outputting first and second series of delayed signals, each delayed signal in each series lagging the input signal more than its predecessor in its respective series, the second series including a portion of the first series and a plurality of signals interpolated therefrom; circuitry for comparing relative phases of at least one of the first and second output signals and the input signal and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output signals from among the respective first and second series of delayed signals in response to the control signals.
Claim 14
Dependent Claim
14 words
The electronic system of claim 10, wherein the electronic system comprises a computer system.
Claim 15
Dependent Claim
18 words
The electronic system of claim 10, wherein the memory device comprises a Synchronous Dynamic Random Access Memory (SDRAM).
Claim 16
Dependent Claim
149 words
A semiconductor substrate having a device fabricated on a surface thereof for outputting first and second output signals, each lagging an input signal by a controlled amount different than the other, the device comprising: circuitry for receiving the input signal and outputting first and second series of delayed signals, each delayed signal in each series lagging the input signal more than its predecessor in its respective series, the second series including a portion of the first series and a plurality of signals interpolated therefrom; circuitry for comparing relative phases of at least one of the first and second output signals and the input signal and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output signals from among the respective first and second series of delayed signals in response to the control signals.
Claim 17
Dependent Claim
149 words
A semiconductor substrate having a device fabricated on a surface thereof for outputting first and second output signals, each lagging an input signal by a controlled amount different than the other, the device comprising: circuitry for receiving the input signal and outputting first and second series of delayed signals, each delayed signal in each series lagging the input signal more than its predecessor in its respective series, the second series including a portion of the first series and a plurality of signals interpolated therefrom; circuitry for comparing relative phases of at least one of the first and second output signals and the input signal and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output signals from among the respective first and second series of delayed signals in response to the control signals.
Claim 18
Dependent Claim
14 words
The semiconductor substrate of claim 13, wherein the semiconductor substrate comprises a semiconductor wafer.
Claim 19
Dependent Claim
205 words
In a circuit for receiving an input signal at a reference phase and outputting a first output signal that lags the input signal by a controlled amount, the circuit having delay elements for outputting a first series of delayed signals, each lagging the input signal by more than its predecessor, the circuit also having a phase detector for comparing relative phases of the first output signal and the input signal and outputting control signals in accordance therewith, a counter for outputting a count in response to the control signals, and a multiplexer for selecting and outputting the first output signal from among the first series of delayed signals in accordance with the count, a device for outputting a second output signal that lags the input signal by a controlled amount, the device comprising: an apparatus for outputting a portion of the first series of delayed signals along with a plurality of interpolated signals in the form of a second series of delayed signals, each lagging the input signal by more than its predecessor; and circuitry coupled to the apparatus for selecting and outputting the second output signal from among the second series of delayed signals in response to the control signals from the phase detector.
Claim 20
Dependent Claim
205 words
In a circuit for receiving an input signal at a reference phase and outputting a first output signal that lags the input signal by a controlled amount, the circuit having delay elements for outputting a first series of delayed signals, each lagging the input signal by more than its predecessor, the circuit also having a phase detector for comparing relative phases of the first output signal and the input signal and outputting control signals in accordance therewith, a counter for outputting a count in response to the control signals, and a multiplexer for selecting and outputting the first output signal from among the first series of delayed signals in accordance with the count, a device for outputting a second output signal that lags the input signal by a controlled amount, the device comprising: an apparatus for outputting a portion of the first series of delayed signals along with a plurality of interpolated signals in the form of a second series of delayed signals, each lagging the input signal by more than its predecessor; and circuitry coupled to the apparatus for selecting and outputting the second output signal from among the second series of delayed signals in response to the control signals from the phase detector.
Claim 21
Dependent Claim
11 words
The device of claim 15, wherein the apparatus comprises interpolation circuitry.
Claim 22
Dependent Claim
15 words
The device of claim 15, wherein the selecting circuitry comprises a counter and a multiplexor.
Claim 23
Dependent Claim
206 words
A delay locked loop for outputting at least first and second output clocks, the delay locked loop comprising: a plurality of delay elements for receiving an input clock and outputting a first series of delayed clocks, each lagging the input clock more than its predecessor; a phase detector for comparing relative phases of the first output clock and the input clock and outputting control signals in accordance therewith; first and second counters coupled to the phase detector for outputting respective first and second counts in response to the control signals; a first multiplexer coupled to the delay elements and the first counter for selecting and outputting the first output clock from among the first series of delayed clocks in accordance with the first count; interpolation circuitry coupled to the delay elements for receiving a portion of the first series of delayed clocks and outputting same along with a plurality of interpolated clocks in the form of a second series of delayed clocks, each lagging the input clock more than its predecessor; and a second multiplexer coupled to the interpolation circuitry and the second counter for selecting and outputting the second output clock from among the second series of delayed clocks in accordance with the second count.
Claim 24
Dependent Claim
206 words
A delay locked loop for outputting at least first and second output clocks, the delay locked loop comprising: a plurality of delay elements for receiving an input clock and outputting a first series of delayed clocks, each lagging the input clock more than its predecessor; a phase detector for comparing relative phases of the first output clock and the input clock and outputting control signals in accordance therewith; first and second counters coupled to the phase detector for outputting respective first and second counts in response to the control signals; a first multiplexer coupled to the delay elements and the first counter for selecting and outputting the first output clock from among the first series of delayed clocks in accordance with the first count; interpolation circuitry coupled to the delay elements for receiving a portion of the first series of delayed clocks and outputting same along with a plurality of interpolated clocks in the form of a second series of delayed clocks, each lagging the input clock more than its predecessor; and a second multiplexer coupled to the interpolation circuitry and the second counter for selecting and outputting the second output clock from among the second series of delayed clocks in accordance with the second count.
Claim 25
Independent Claim
119 words
A method for generating first and second output signals, each lagging an input signal by a controlled amount different than the other, the method comprising: generating a first series of delayed signals, each lagging the input signal more than its predecessor; generating a second series of delayed signals, each lagging the input signal more than its predecessor, the second series including a portion of the first series and a plurality of signals interpolated therefrom; comparing relative phases of at least one of the first and second output signals and the input signal; and selecting and outputting the first and second output signals from among the respective first and second series of delayed signals in accordance with the phase comparison.
Claim 26
Independent Claim
119 words
A method for generating first and second output signals, each lagging an input signal by a controlled amount different than the other, the method comprising: generating a first series of delayed signals, each lagging the input signal more than its predecessor; generating a second series of delayed signals, each lagging the input signal more than its predecessor, the second series including a portion of the first series and a plurality of signals interpolated therefrom; comparing relative phases of at least one of the first and second output signals and the input signal; and selecting and outputting the first and second output signals from among the respective first and second series of delayed signals in accordance with the phase comparison.
Claim 27
Dependent Claim
31 words
The method of claim 19, wherein the acts of generating the first and second series of delayed signals comprise generating said series using a plurality of delay elements and interpolation circuitry.
Claim 28
Independent Claim
251 words
A device for generating a quadrature clock signal, the device comprising: a delay circuit configured to receive an input signal and produce first and second series of signals in response thereto, each signal in each series of signals lagging the input signal by an amount different than the other signals; an interpolation circuit coupled to the delay circuit and configured to receive the second series of signals and produce a third series of signals, the third series of signals including a majority of the second series of signals and at least one additional signal between every adjacent pair of signals of the second series of signals such that the at least one signal lags the input signal by an amount greater than a first signal of the adjacent pair of signals, but less than a second signal of the adjacent pair of signals; a first selection circuit coupled to the delay-circuit and configured to select and output a first signal from the first series of signals; a second selection circuit coupled to the interpolation circuit and configured to select and output a second signal from the third series of signals; and a phase comparing circuit coupled to the first and second selection circuits and configured to compare the respective phases of at least one of the first signal from the first series of signals and the second signal from the third series of signals with the input signal and to relay selection control signals to the first and second selection circuits.
Claim 29
Independent Claim
251 words
A device for generating a quadrature clock signal, the device comprising: a delay circuit configured to receive an input signal and produce first and second series of signals in response thereto, each signal in each series of signals lagging the input signal by an amount different than the other signals; an interpolation circuit coupled to the delay circuit and configured to receive the second series of signals and produce a third series of signals, the third series of signals including a majority of the second series of signals and at least one additional signal between every adjacent pair of signals of the second series of signals such that the at least one signal lags the input signal by an amount greater than a first signal of the adjacent pair of signals, but less than a second signal of the adjacent pair of signals; a first selection circuit coupled to the delay-circuit and configured to select and output a first signal from the first series of signals; a second selection circuit coupled to the interpolation circuit and configured to select and output a second signal from the third series of signals; and a phase comparing circuit coupled to the first and second selection circuits and configured to compare the respective phases of at least one of the first signal from the first series of signals and the second signal from the third series of signals with the input signal and to relay selection control signals to the first and second selection circuits.
Claim 30
Dependent Claim
33 words
The device of claim 21, wherein the first selection circuit is configured to select a first signal from the first series of signals which is 180° out of phase with the input signal.
Claim 31
Dependent Claim
33 words
The device of claim 21, wherein the second selection circuit is configured to select a second signal from the third series of signals which is 90° out of phase with the input signal.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-24 | 2004-04-24 | 2004-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-24 | 2008-04-24 | 2008-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-24 | 2012-04-24 | 2012-10-24 | $7700.00 | Window Closed / Lapsed |