US5644538A
Expired / Lapsed
US
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Circuit and method for controllng the duration of pulses in a control signal from an electronic system
Assignee: Micron Technology Inc
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Filing: 1996-03-01
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Granted: 1997-07-01
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Expires: 2016-03-01
Abstract
Abstract A memory device (10) for use in an electronic system (12). The system (12) includes a processor (16) that produces a plurality of control signals. The memory device (10) includes a memory array (18) coupled to receive control signals from the processor (18). The memory device (10) also includes a pulse generator (22) that receives at least one of the control signals from the processor (16). The pulse generator (22) includes a latch formed from, for example, a cross coupled pair of NAND-gates (32 and 34). A delayed signal from the latch is coupled to control the reset of the latch such that the latch of the pulse generator (22) outputs a modified control signal for the memory device (10) that has a pulse with a width that is at least as long as the delay.
Inventors
- 👤 Todd A. Merritt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:06
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C8/00; G11C8/18; H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/13; H03K5/153; H03K5/1534; H03K5/156
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
101 words
A memory device for use with an electronic system, the memory device comprising: pulse generator including: a first lockout circuit that extends a low logic pulse of the control signal to produce an acceptable control signal; a second lockout circuit that extends a high logic pulse of the control signal to produce an acceptable control signal; and a logic gate coupled to receive the output of each of the first and second lockout circuits for outputting the generated control signal for the memory device; and a memory array with an address circuit coupled to receive the control signal from pulse generator.
Claim 2
Dependent Claim
101 words
A memory device for use with an electronic system, the memory device comprising: pulse generator including: a first lockout circuit that extends a low logic pulse of the control signal to produce an acceptable control signal; a second lockout circuit that extends a high logic pulse of the control signal to produce an acceptable control signal; and a logic gate coupled to receive the output of each of the first and second lockout circuits for outputting the generated control signal for the memory device; and a memory array with an address circuit coupled to receive the control signal from pulse generator.
Claim 3
Dependent Claim
45 words
The memory device of claim 1, wherein the first and second lockout circuits each include a delay circuit coupled between the output of the lockout circuit and a reset input so as to establish the width of the pulse generated by the respective lockout circuits.
Claim 4
Dependent Claim
24 words
The memory device of claim 1, wherein the pulse generator receives a column address strobe signal from the electronic system as the control signal.
Claim 5
Dependent Claim
19 words
The memory device of claim 1, wherein the memory device comprises an extended data out dynamic random access memory.
Claim 6
Dependent Claim
20 words
The memory device of claim 1, wherein the memory device comprises a burst extended data out dynamic random access memory.
Claim 7
Dependent Claim
21 words
The memory device of claim 1, wherein the pulse generator receives a clock signal for a sync dynamic random access memory.
Claim 8
Dependent Claim
57 words
A pulse generator, comprising: a latch coupled to receive a pulsed signal from an external source, the latch including first and second outputs; and a delay circuit coupled between the first output of the latch and a reset input of the latch such that the second output of the latch provides pulses of substantially the same duration.
Claim 9
Dependent Claim
57 words
A pulse generator, comprising: a latch coupled to receive a pulsed signal from an external source, the latch including first and second outputs; and a delay circuit coupled between the first output of the latch and a reset input of the latch such that the second output of the latch provides pulses of substantially the same duration.
Claim 10
Dependent Claim
13 words
The pulse generator of claim 7, wherein the latch comprises a flip-flop circuit.
Claim 11
Dependent Claim
19 words
The pulse generator of claim 7, wherein the latch comprises a pair of NAND-gates in a cross coupled configuration.
Claim 12
Dependent Claim
35 words
The pulse generator of claim 7, wherein the delay circuit comprises a circuit that delays the reset signal when the output of the latch transitions from a low logic level to a high logic level.
Claim 13
Dependent Claim
21 words
The pulse generator of claim 7, wherein the delay circuit introduces at least a 3 nanosecond delay into the reset signal.
Claim 14
Dependent Claim
69 words
The pulse generator of claim 7, wherein the delay circuit comprises: an inverter coupled to a second input of the latch; and a delay circuit coupled between a first output of the latch and the input of the inverter so as to delay a reset signal to the latch by a period of time such that the second output of the latch provides pulses of substantially the same duration.
Claim 15
Dependent Claim
170 words
A pulse generator comprising: a first latch coupled to receive a pulsed signal from an external source, the latch including an output and a reset input; a first delay circuit coupled between the output of the first latch and the reset input of the first latch such that the first latch produces pulses of a first logic level with a duration that is at least as long as a delay of the delay circuit; a second latch that is coupled to the output of the first latch, the second latch having an output and a reset input; a second delay circuit coupled between an output of the second latch and a reset input of the second latch such that the second latch outputs a modified control signal that has a pulse with a duration that is at least as long as a delay of the second delay circuit; and a logic circuit coupled to the outputs of the first and second latches that generates an output for the pulse generator.
Claim 16
Dependent Claim
170 words
A pulse generator comprising: a first latch coupled to receive a pulsed signal from an external source, the latch including an output and a reset input; a first delay circuit coupled between the output of the first latch and the reset input of the first latch such that the first latch produces pulses of a first logic level with a duration that is at least as long as a delay of the delay circuit; a second latch that is coupled to the output of the first latch, the second latch having an output and a reset input; a second delay circuit coupled between an output of the second latch and a reset input of the second latch such that the second latch outputs a modified control signal that has a pulse with a duration that is at least as long as a delay of the second delay circuit; and a logic circuit coupled to the outputs of the first and second latches that generates an output for the pulse generator.
Claim 17
Independent Claim
72 words
A method for modifying a pulse width of a signal, comprising the steps of: receiving the signal from an external source; providing the signal to a latch; generating a reset signal for the latch by providing a first output of the latch to a reset input of the latch through a delay circuit such that a second output of the latch provides a modified signal with pulses of substantially the same duration.
Claim 18
Independent Claim
72 words
A method for modifying a pulse width of a signal, comprising the steps of: receiving the signal from an external source; providing the signal to a latch; generating a reset signal for the latch by providing a first output of the latch to a reset input of the latch through a delay circuit such that a second output of the latch provides a modified signal with pulses of substantially the same duration.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-30 | 2000-12-30 | 2001-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-30 | 2004-12-30 | 2005-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-30 | 2008-12-30 | 2009-07-01 | $7700.00 | Window Closed / Lapsed |