Integrated circuit memory having a self-timed write pulse independent of clock frequency and duty cycle

Claim 2

An integrated circuit memory, comprising: a plurality of memory cells, a memory cell of the plurality of memory cells coupled to a bit line and to a word line; a write logic circuit, coupled to the plurality of memory cells, for providing a data signal to the bit line in response to a write pulse, the data signal corresponding to input data; and a write pulse circuit, coupled to the write logic circuit, for providing the write pulse during a write cycle of the integrated circuit memory, the write pulse being triggered by an edge of an input clock signal, and the write pulse having a duration determined by a predetermined delay, wherein the duration of the write pulse is independent of the input clock signal duty cycle and frequency.

Claim 3

The integrated circuit memory of claim 1, wherein the write pulse circuit comprises: a first logic gate having a first input terminal for receiving the input clock signal, a second input terminal, and an output terminal; a first delay element having an input terminal for receiving the input clock signal, and an output terminal; a first inverter having an input terminal coupled to the output terminal of the first delay element, and an output terminal coupled to the second input terminal of the first logic gate; a second inverter having an input terminal coupled to the output terminal of the first logic gate, and an output terminal; a second logic gate having a first input terminal coupled to the output terminal of the second inverter, a second input terminal, and an output terminal; a third logic gate having a first input terminal coupled to the output terminal of the second logic gate, a second input terminal, and an output terminal coupled to the second input terminal of the second logic gate; and a second delay element having an input terminal coupled to the output terminal of the third logic gate, and an output terminal coupled to the second input terminal of the third logic gate.

Claim 4

The integrated circuit memory of claim 2, wherein the predetermined delay is determined by a delay provided by the second delay element.

Claim 5

The integrated circuit memory of claim 2, wherein the first delay element provides a first delay time and the second delay element provides a second delay time, the first delay time equal to about one-half of the second delay time.

Claim 6

The integrated circuit memory of claim 2, wherein the first and second delay elements are characterized as being single-sided delay elements.

Claim 7

The integrated circuit memory of claim 2, wherein the first logic gate provides a logical NAND function and the second and third logic gates provide a logical NOR function.

Claim 8

An integrated circuit memory, comprising: a plurality of memory cells, a memory cell of the plurality of memory cells coupled to a bit line and to a word line; a write logic circuit, coupled to the plurality of memory cells, for providing a data signal to the bit line in response to a write pulse, the data signal corresponding to input data; and a write pulse generator, coupled to the write logic circuit, the write pulse generator receiving a clock signal and a write enable signal of a predetermined logic state, and in response, the write pulse generator providing the write pulse during a write cycle of the integrated circuit memory, the write pulse being triggered by a rising edge of the clock signal, and the write pulse having a duration determined by a predetermined delay, wherein the duration of the write pulse is independent of the input clock signal duty cycle and frequency.

Claim 9

An integrated circuit memory, comprising: a plurality of memory cells, a memory cell of the plurality of memory cells coupled to a bit line and to a word line; a write logic circuit, coupled to the plurality of memory cells, for providing a data signal to the bit line in response to a write pulse, the data signal corresponding to input data; and a write pulse generator, coupled to the write logic circuit, the write pulse generator receiving a clock signal and a write enable signal of a predetermined logic state, and in response, the write pulse generator providing the write pulse during a write cycle of the integrated circuit memory, the write pulse being triggered by a rising edge of the clock signal, and the write pulse having a duration determined by a predetermined delay, wherein the duration of the write pulse is independent of the input clock signal duty cycle and frequency.

Claim 10

The integrated circuit memory of claim 7, wherein the plurality of memory cells are characterized as being a plurality of static random access memory cells.

Claim 11

The integrated circuit memory of claim 7, wherein the write pulse generator comprises: a first logic gate having a first input terminal for receiving the clock signal, a second input terminal, and an output terminal; a first delay element having an input terminal for receiving the clock signal, and an output terminal; a first inverter having an input terminal coupled to the output terminal of the first delay element, and an output terminal coupled to the second input terminal of the first logic gate; a second inverter having an input terminal coupled to the output terminal of the first logic gate, and an output terminal; a second logic gate having a first input terminal coupled to the output terminal of the second inverter, a second input terminal, and an output terminal; a third logic gate having a first input terminal coupled to the output terminal of the second logic gate, a second input terminal, and an output terminal coupled to the second input terminal of the second logic gate; and a second delay element having an input terminal coupled to the output terminal of the third logic gate, and an output terminal coupled to the second input terminal of the third logic gate.

Claim 12

The integrated circuit memory of claim 9, wherein the predetermined delay is determined by the second delay element.

Claim 13

The integrated circuit memory of claim 9, wherein the first delay element provides a first delay time and the second delay element provides a second delay time, the first delay time equal to about one-half of the second delay time.

Claim 14

The integrated circuit memory of claim 9, wherein the first and second delay elements are characterized as being single-sided delay elements.

Claim 15

The integrated circuit memory of claim 9, wherein the first logic gate provides a logical NAND function and the second and third logic gates provide a logical NOR function.

Claim 16

The integrated circuit memory of claim 9, further comprising: a fourth logic gate having a first input terminal coupled to the output terminal of the third logic gate, a second input terminal for receiving a chip select signal, and an output terminal; and a fifth logic gate having a first input terminal coupled to the output terminal of the fourth logic gate, a second input terminal for receiving a write enable signal, and an output terminal coupled to the write logic circuit.

Claim 17

An integrated circuit memory, comprising: a plurality of memory cells, a memory cell of the plurality of memory cells coupled to a bit line and to a word line; a write logic circuit, coupled to the plurality of memory cells, for providing a data signal to the bit line in response to a write pulse, the data signal corresponding to input data; and a write pulse generator coupled to the write logic circuit, the write pulse generator comprising: a first logic gate having a first input terminal for receiving an input clock signal, a second input terminal, and an output terminal; a first delay element having an input terminal for receiving the input clock signal, and an output terminal; a first inverter having an input terminal coupled to the output terminal of the first delay element, and an output terminal coupled to the second input terminal of the first logic gate; a second inverter having an input terminal coupled to the output terminal of the first logic gate, and an output terminal; a second logic gate having a first input terminal coupled to the output terminal of the second inverter, a second input terminal, and an output terminal; a third logic gate having a first input terminal coupled to the output terminal of the second logic gate, a second input terminal, and an output terminal coupled to the second input terminal of the second logic gate for providing the write pulse; and a second delay element having an input terminal coupled to the output terminal of the third logic gate, and an output terminal coupled to the second input terminal of the third logic gate.

Claim 18

An integrated circuit memory, comprising: a plurality of memory cells, a memory cell of the plurality of memory cells coupled to a bit line and to a word line; a write logic circuit, coupled to the plurality of memory cells, for providing a data signal to the bit line in response to a write pulse, the data signal corresponding to input data; and a write pulse generator coupled to the write logic circuit, the write pulse generator comprising: a first logic gate having a first input terminal for receiving an input clock signal, a second input terminal, and an output terminal; a first delay element having an input terminal for receiving the input clock signal, and an output terminal; a first inverter having an input terminal coupled to the output terminal of the first delay element, and an output terminal coupled to the second input terminal of the first logic gate; a second inverter having an input terminal coupled to the output terminal of the first logic gate, and an output terminal; a second logic gate having a first input terminal coupled to the output terminal of the second inverter, a second input terminal, and an output terminal; a third logic gate having a first input terminal coupled to the output terminal of the second logic gate, a second input terminal, and an output terminal coupled to the second input terminal of the second logic gate for providing the write pulse; and a second delay element having an input terminal coupled to the output terminal of the third logic gate, and an output terminal coupled to the second input terminal of the third logic gate.

Claim 19

The integrated circuit memory of claim 15, further comprising a fourth logic gate having a first input-terminal coupled to the output terminal of the third logic gate, a second input terminal for receiving a chip select signal, and an output terminal.

Claim 20

The integrated circuit memory of claim 16, further comprising a fifth logic gate having a first input terminal coupled to the output terminal of the fourth logic gate, a second input terminal for receiving a write enable signal, and an output terminal coupled to the write logic circuit.

Claim 21

The integrated circuit memory of claim 15, wherein the first and second delay elements are characterized as being single-sided delay elements.

Claim 22

The integrated circuit memory of claim 15, wherein the first delay element provides a first delay time and the second delay element provides a second delay time, the first delay time equal to about one-half of the second delay time.

Claim 23

The integrated circuit memory of claim 15, further comprising: a fourth logic gate having a first input terminal coupled to the output terminal of the third logic gate, a second input terminal for receiving a chip select signal, and an output terminal; and a fifth logic gate having a first input terminal coupled to the output terminal of the fourth logic gate, a second input terminal for receiving a write enable signal, and an output terminal coupled to the write logic circuit.