Latched type clock synchronizer with additional 180°-phase shift clock

Claim 2

A latched type clock synchronizer circuit to provide multiple phases of an internal clock for an integrated circuit that is synchronized to an external system clock, such that said internal clock has minimal skew with said external system clock and the multiple phases are aligned, comprising a) an input buffer circuit to receive, buffer, and amplify said external input clock to create a first timing clock; b) a delay monitor circuit connected to the input buffer to delay the first timing clock by a first delay factor to create a second timing clock; c) a delay measurement latch array connected to the input buffer circuit and the delay monitor circuit to create a latched measurement signal indicating a period of time between a second pulse of the first timing clock and a first pulse of the second timing clock; d) a multiple delay array connected to the input buffer to receive the first timing signal to create multiple pluralities of incrementally delayed timing clocks; e) a plurality of phase generators to create a plurality of third timing clocks whereby each phase generator is connected to the delay measurement latch array to receive the latched measurement signal and to the multiple delay array to receive one of the plurality of incrementally delay timing clocks, such that the latched measurement signal will select one of the incrementally delayed timing clocks to create the third timing clock; and f) a plurality of internal buffers whereby each internal buffer is connected to one of the phase generators to receive one of the third timing clocks, shape said third timing clock to create one of the multiple phases of the internal clocks and to buffer, amplify and transmit said phase of the internal clock to said integrated circuit, whereby said internal buffer has a second delay time to synchronize said phase with said external system clock.

Claim 3

The latched type clock synchronizer circuit of claim 1 wherein said integrated circuit is a synchronous dynamic random access memory and said internal clock will control a transfer of digital data to and from said synchronous dynamic random access memory.

Claim 4

The latched type clock synchronizer circuit of claim 1 wherein said delay factor is twice the first delay time plus the second delay time.

Claim 5

The latched type clock synchronizer circuit of claim 1 wherein the delay measurement latch array comprises a first latched delay element and a plurality of serially cascaded delay elements whereby each latched delay element includes: a) a first clock input connected to the input buffer to receive the first timing clock; b) a second clock input such that said second input of the first latched delay element is connected to the delay monitor circuit to receive the second timing clock; c) a delay gate connected to the second input to delay the second timing clock; d) an alignment checking latch that will be set when the second pulse of the first timing clock is aligned with the first pulse of the delayed second clock; and e) a delay output connected to the delay gate to transmit the delayed second clock to the second input of a following latched delay element of the plurality of cascaded latched delay elements.

Claim 6

The latched type clock synchronizer circuit of claim 1 wherein the multiple delay array comprises multiple first delay elements and multiple pluralities of serially connected delay elements with each plurality connected to one of the first delay elements, whereby each delay element comprises: a) a delay element input such that said delay element input of each first delay element is connected to the input buffer to receive the first timing clock; b) a second delay gate connected to the delay element input to delay the first timing clock; c) a first delay element output connected to the second delay gate to transmit a delay first timing clock to subsequent delay elements; and d) a delay tap output to transmit one of the delayed timing clocks.

Claim 7

The latched type clock synchronizer circuit of claim 1 wherein each of the plurality of phase generators comprises a plurality of logic gates wherein each logic gate will logically combine the latched measurement signal with one of the multiple pluralities of delay timing signals to create one of the third timing clocks.

Claim 8

A synchronous dynamic random access memory to retain digital data comprising: a) a plurality of memory banks in which to retain said digital data; b) an address control buffer connected to a system address bus to receive an address and to the plurality of memory banks to select a location of said digital data within said plurality of memory banks; c) a command decoder connected to a command bus to receive and interpret system commands for said synchronous dynamic random access memory and connected to the plurality of memory banks to transfer said commands to said memory banks; d) a data control circuit connected to the plurality of memory banks to control a flow of said digital data; e) a data input/output buffer connected to a system data bus and to said data control circuit to receive and transmit said digital data from said system data bus to said data control circuit; and f) a clock buffer circuit connected to a system input clock to create a plurality of internal clocking signals including multiple phases of a synchronized internal clock, comprising: an input buffer circuit to receive, buffer, and amplify said external input clock to create a first timing clock, a delay monitor circuit connected to the input buffer to delay the first timing clock by a first delay factor to create a second timing clock, a delay measurement latch array connected to the input buffer circuit and the delay monitor circuit to create a latched measurement signal indicating a period of time between a second pulse of the first timing clock and a first pulse of the second timing clock, a multiple delay array connected to the input buffer to receive the first timing signal to create multiple pluralities of incrementally delayed timing clocks, a plurality of phase generators to create a plurality of third timing clocks whereby each phase generator is connected to the delay measurement latch array to receive the latched measurement signal and to the multiple delay array to receive one of the plurality of incrementally delay timing clocks, such that the latched measurement signal will select one of the incrementally delayed timing clocks to create the third timing clock, and a plurality of internal buffers whereby each internal buffer is connected to one of the phase generators to receive one of the third timing clocks, shape said third timing clock to create one of the multiple phases of the internal clocks and to buffer, amplify and transmit said phase of the internal clock to said integrated circuit, whereby said internal buffer has a second delay time to synchronize said phase with said external system clock.

Claim 9

A synchronous dynamic random access memory to retain digital data comprising: a) a plurality of memory banks in which to retain said digital data; b) an address control buffer connected to a system address bus to receive an address and to the plurality of memory banks to select a location of said digital data within said plurality of memory banks; c) a command decoder connected to a command bus to receive and interpret system commands for said synchronous dynamic random access memory and connected to the plurality of memory banks to transfer said commands to said memory banks; d) a data control circuit connected to the plurality of memory banks to control a flow of said digital data; e) a data input/output buffer connected to a system data bus and to said data control circuit to receive and transmit said digital data from said system data bus to said data control circuit; and f) a clock buffer circuit connected to a system input clock to create a plurality of internal clocking signals including multiple phases of a synchronized internal clock, comprising: an input buffer circuit to receive, buffer, and amplify said external input clock to create a first timing clock, a delay monitor circuit connected to the input buffer to delay the first timing clock by a first delay factor to create a second timing clock, a delay measurement latch array connected to the input buffer circuit and the delay monitor circuit to create a latched measurement signal indicating a period of time between a second pulse of the first timing clock and a first pulse of the second timing clock, a multiple delay array connected to the input buffer to receive the first timing signal to create multiple pluralities of incrementally delayed timing clocks, a plurality of phase generators to create a plurality of third timing clocks whereby each phase generator is connected to the delay measurement latch array to receive the latched measurement signal and to the multiple delay array to receive one of the plurality of incrementally delay timing clocks, such that the latched measurement signal will select one of the incrementally delayed timing clocks to create the third timing clock, and a plurality of internal buffers whereby each internal buffer is connected to one of the phase generators to receive one of the third timing clocks, shape said third timing clock to create one of the multiple phases of the internal clocks and to buffer, amplify and transmit said phase of the internal clock to said integrated circuit, whereby said internal buffer has a second delay time to synchronize said phase with said external system clock.

Claim 10

The synchronous dynamic random access memory of claim 7 wherein the delay measurement latch array comprises a first latched delay element and a plurality of serially cascaded delay elements whereby each latched delay element includes: a) a first clock input connected to the input buffer to receive the first timing clock; b) a second clock input such that said second input of the first latched delay element is connected to the delay monitor circuit to receive the second timing clock; c) a delay gate connected to the second input to delay the second timing clock; d) an alignment checking latch that will be set when the second pulse of the first timing clock is aligned with the first pulse of the delayed second clock; and e) a delay output connected to the delay gate to transmit the delayed second clock to the second input of a following latched delay element of the plurality of cascaded latched delay elements.

Claim 11

The synchronous dynamic random access memory of claim 7 wherein the multiple delay array comprises multiple first delay elements and multiple pluralities of serially connected delay elements with each plurality connected to one of the first delay elements, whereby each delay element comprises: a) a delay element input such that said delay element input of each first delay element is connected to the input buffer to receive the first timing clock; b) a second delay gate connected to the delay element input to delay the first timing clock; c) a first delay element output connected to the second delay gate to transmit a delay first timing clock to subsequent delay elements; and d) a delay tap output to transmit one of the delayed timing clocks.

Claim 12

The synchronous dynamic random access memory of claim 7 wherein each of the plurality of phase generators comprises a plurality of logic gates wherein each logic gate will logically combine the latched measurement signal with one of the multiple pluralities of delay timing signals to create one of the third timing clocks.