US5489864A
Expired / Lapsed
US
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Delay interpolation circuitry
Assignee: Intel Corp
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Filing: 1995-02-24
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Granted: 1996-02-06
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Expires: 2015-02-24
Abstract
Abstract An integrated circuit for deskewing and adjusting a delay of a synthesized waveform. The synthesized waveform is initially produced by a digital-to-time domain converter which is coupled to a synchronous delay line and a pattern ROM through a shifter and a pattern register. The synchronous delay line generates a plurality of taps in response to a reference signal. Each one of the taps has a unit delay and is coupled to the digital-to-time domain converter. The integrated circuit which deskews and adjusts the delay of the synthesized waveform comprises a microdelay calibration circuit, a deskew control circuit, and a delay interpolation circuit. The microdelay calibration circuit is coupled to the taps of the synchronous delay line and the deskew control circuit. The deskew control circuit is coupled the shifter to perform coarse deskew operations. The deskew control circuit is further coupled to the delay interpolation circuit to perform fine deskew operations. The output of the digital to time domain converter is coupled to the delay interpolation circuit which then outputs a deskewed synthesized waveform. Deskew resolution of 0.05 ns is achieved with the integrated circuit described herein.
Inventors
- 👤 Roni Ashuri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:19
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
130 words
An integrated circuit for deskewing a synthesized waveform, the synthesized waveform being generated by a first digital-to-time domain converter in response to a pattern received from a shifter, the first digital-to-time domain converter being coupled to a synchronous delay line, the synchronous delay line generating a plurality of taps in response to a reference signal, each one of the plurality of taps coupled to the first digital-to-time domain converter, each one of the plurality of taps having a unit delay, the integrated circuit comprising: a calibration circuit coupled to the synchronous delay line; a delay interpolation circuit coupled to the first digital-to-time domain converter, the delay interpolation circuit generating a deskewed synthesized waveform; and a deskew control circuit coupled to the calibration circuit, the shifter, and the delay interpolation circuit.
Claim 2
Dependent Claim
130 words
An integrated circuit for deskewing a synthesized waveform, the synthesized waveform being generated by a first digital-to-time domain converter in response to a pattern received from a shifter, the first digital-to-time domain converter being coupled to a synchronous delay line, the synchronous delay line generating a plurality of taps in response to a reference signal, each one of the plurality of taps coupled to the first digital-to-time domain converter, each one of the plurality of taps having a unit delay, the integrated circuit comprising: a calibration circuit coupled to the synchronous delay line; a delay interpolation circuit coupled to the first digital-to-time domain converter, the delay interpolation circuit generating a deskewed synthesized waveform; and a deskew control circuit coupled to the calibration circuit, the shifter, and the delay interpolation circuit.
Claim 3
Dependent Claim
39 words
The integrated circuit described in claim 1 wherein the delay interpolation circuit outputs the deskewed synthesized waveform on an output signal line, the delay interpolation circuit comprising a first plurality of microdelay elements attached to the output signal line.
Claim 4
Dependent Claim
29 words
The integrated circuit described in claim 2 wherein the deskew control circuit selectively activates each one of the first plurality of microdelay elements through a fine adjust signal line.
Claim 5
Dependent Claim
35 words
The integrated circuit described in claim 3 wherein the deskew control circuit receives a count signal from the calibration circuit, the count signal representing a number of microdelay elements substantially equivalent to the unit delay.
Claim 6
Dependent Claim
51 words
The integrated circuit described in claim 4 wherein the deskew control circuit is coupled to the shifter through a coarse adjust signal line, the shifter being coupled to the first digital-to-time domain converter through a first pattern register, the deskew control circuit outputting a coarse adjust signal to the shifter circuit.
Claim 7
Dependent Claim
39 words
The integrated circuit described in claim 5 wherein the shifter shifts the pattern in response to the coarse adjust signal, the synthesized waveform being phase shifted when the shifter shifts the pattern in response to the coarse adjust signal.
Claim 8
Dependent Claim
74 words
The integrated circuit described in claim 6 wherein the deskew control circuit increases the delay of the synthesized waveform by the unit delay when the number of microdelay elements substantially equivalent to the unit delay have been activated, the deskew control circuit deactivating all of the first plurality of microdelay elements after the delay of the synthesized waveform is increased by the unit delay with the shifter in response to the course adjust signal.
Claim 9
Dependent Claim
69 words
The integrated circuit described in claim 7 wherein the deskew control circuit decreases the delay of the synthesized waveform by the unit delay when no microdelay elements have been activated, the deskew control circuit activating the number of microdelay elements substantially equivalent to the unit delay after the delay of the synthesized waveform is decreased by the unit delay with the shifter in response to the course adjust signal.
Claim 10
Dependent Claim
78 words
The integrated circuit described in claim 8 wherein the calibration circuit comprises: a reference path circuit coupled to the synchronous delay line, the reference path circuit synthesizing a reference path waveform; a calibrated path circuit coupled to the synchronous delay line, the calibrated path circuit synthesizing a calibrated path waveform; a phase detector receiving the reference path waveform and the calibrated path waveform; and a second control circuit coupled to the phase detector and the calibrated path circuit.
Claim 11
Dependent Claim
68 words
The integrated circuit described in claim 9 wherein the reference path circuit comprises: a second digital-to-time domain converter coupled to the synchronous delay line, the second digital-to-time domain converter synthesizing the reference path waveform through a reference path signal line; and a rotate-by-1 rotator coupled to the second digital-to-time domain converter and a pattern ROM, the rotate-by-1 rotator introducing the one unit delay into the reference path waveform.
Claim 12
Dependent Claim
96 words
The integrated circuit described in claim 10 wherein the calibrated path circuit comprises: a third digital-to-time domain converter coupled to the synchronous delay line and the pattern ROM, the third digital-to-time domain converter synthesizing the calibrated path waveform through a calibrated path signal line; and a second plurality of microdelay elements attached to the calibrated path signal line, the second plurality of microdelay elements selectively activated and deactivated by the second control circuit in response to the phase detector, the second plurality of microdelay elements adding a first parasitic load to the calibrated path signal line.
Claim 13
Dependent Claim
29 words
The integrated circuit described in claim 11 wherein the phase detector indicates when there is substantially no phase difference between the reference path waveform and the calibrated path waveform.
Claim 14
Dependent Claim
22 words
The integrated circuit described in claim 12 wherein the second control circuit generates the count signal in response to the phase detector.
Claim 15
Dependent Claim
32 words
The integrated circuit described in claim 13 wherein a second parasitic load is coupled to the reference path signal line, the second parasitic load being substantially equal to the first parasitic load.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-05 | 1999-08-07 | 2000-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-05 | 2003-08-07 | 2004-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-05 | 2007-08-07 | 2008-02-06 | $7700.00 | Window Closed / Lapsed |