US6137334A
Expired / Lapsed
US
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Logic circuit delay stage and delay line utilizing same
Assignee: Micron Technology Inc
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Filing: 1998-07-06
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Granted: 2000-10-24
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Expires: 2018-07-06
Abstract
Abstract The present invention is embodied in a method and apparatus for improving a delay line circuit of a Digital Delay Lock Loop (DDLL) circuit. Each delay stage of the delay line consists of three gates, two NANDs and one inverter. The reduction in the total number of gates decreases the unit delay time for each stage, improving the resolution of each stage of the delay line. In addition, the reduction in the total number of gates in each stage significantly reduces the amount of space necessary for the circuitry of the delay line, resulting in an overall decrease in the size of the DDLL circuit.
Inventors
- 👤 James E. Miller, Jr.
- 👤 Aaron Schoenfeld
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:53
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03K; H03K5/00; H03K5/13; H03K5/135; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
133 words
A logic circuit delay stage of a delay line, said logic circuit delay stage comprising: a first logic circuit having an input and an output, said input directly connected to a first input signal and said output directly connected to a first output of said delay stage; a second logic circuit having a first input, a second input, and an output, said first input being directly connected to a precharge signal, said output being directly connected to a second output of said delay stage; and a switch directly connected between said first input signal and said second input of said second logic circuit, whereby a control signal will cause said switch to open or close to determine a path of said first input signal, thereby controlling a delay of said first input signal.
Claim 2
Dependent Claim
133 words
A logic circuit delay stage of a delay line, said logic circuit delay stage comprising: a first logic circuit having an input and an output, said input directly connected to a first input signal and said output directly connected to a first output of said delay stage; a second logic circuit having a first input, a second input, and an output, said first input being directly connected to a precharge signal, said output being directly connected to a second output of said delay stage; and a switch directly connected between said first input signal and said second input of said second logic circuit, whereby a control signal will cause said switch to open or close to determine a path of said first input signal, thereby controlling a delay of said first input signal.
Claim 3
Dependent Claim
17 words
The logic circuit delay stage according to claim 1, wherein said first logic circuit is an inverter.
Claim 4
Dependent Claim
18 words
The logic circuit delay stage according to claim 2, wherein said second logic circuit is a NAND gate.
Claim 5
Dependent Claim
16 words
The logic circuit delay stage according to claim 3, wherein said switch is a NAND gate.
Claim 6
Dependent Claim
18 words
The logic circuit delay stage according to claim 1, wherein a unit delay time is approximately 50 picoseconds.
Claim 7
Dependent Claim
19 words
The logic circuit delay stage according to claim 1, wherein said control signal is provided by a shift register.
Claim 8
Dependent Claim
144 words
A delay line for controlling a delay of an input signal, said delay line comprising: at least one delay stage, each of said delay stages comprising: a first logic circuit having an input and an output, said input directly connected to a first input signal and said output directly connected to a first output of said delay stage; a second logic circuit having a first input, a second input, and an output, said first input being directly connected to a precharge signal, said output being directly connected to a second output of said delay stage; and a switch directly connected between said first input signal and said second input of said second logic circuit, whereby a control signal will cause said switch to open or close to determine a path of said first input signal, thereby controlling a delay of said first input signal.
Claim 9
Dependent Claim
144 words
A delay line for controlling a delay of an input signal, said delay line comprising: at least one delay stage, each of said delay stages comprising: a first logic circuit having an input and an output, said input directly connected to a first input signal and said output directly connected to a first output of said delay stage; a second logic circuit having a first input, a second input, and an output, said first input being directly connected to a precharge signal, said output being directly connected to a second output of said delay stage; and a switch directly connected between said first input signal and said second input of said second logic circuit, whereby a control signal will cause said switch to open or close to determine a path of said first input signal, thereby controlling a delay of said first input signal.
Claim 10
Dependent Claim
15 words
The delay line according to claim 7, wherein said first logic circuit is an inverter.
Claim 11
Dependent Claim
16 words
The delay line according to claim 8, wherein said second logic circuit is a NAND gate.
Claim 12
Dependent Claim
14 words
The delay line according to claim 9, wherein said switch is a NAND gate.
Claim 13
Dependent Claim
35 words
The delay line according to claim 7, wherein said precharge signal for a delay stage other than a first of said at least one delay stages is said second output from a preceding delay stage.
Claim 14
Dependent Claim
25 words
The delay line according to claim 7, wherein a unit delay time for each of said at least one delay stage is approximately 50 picoseconds.
Claim 15
Dependent Claim
17 words
The delay line according to claim 7, wherein said control signal is provided by a shift register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-24 | 2004-04-24 | 2004-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-24 | 2008-04-24 | 2008-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-24 | 2012-04-24 | 2012-10-24 | $7700.00 | Window Closed / Lapsed |