US6069506A
Expired / Lapsed
US
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Method and apparatus for improving the performance of digital delay locked loop circuits
Assignee: Micron Technology Inc
•
Filing: 1998-05-20
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Granted: 2000-05-30
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Expires: 2018-05-20
Abstract
Abstract A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.
Inventors
- 👤 James E. Miller, Jr.
- 👤 Aaron Schoenfeld
- 👤 Manny Ma
- 👤 R. Jacob Baker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:31
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/10; H03K; H03K5/00; H03K5/13; H03K5/133; H03L7/0816
Claims Analysis
Total Claims: 58
Claim 1
Independent Claim
177 words
A computer system comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop for synchronizing the required clock signals for said integrated circuits, said delay locked loop comprising: a phase detect circuit for comparing the phases of an input and output clock signal and for outputting a control signal based on said comparison; a delay line coupled to said input clock signal and a shift register, said delay line controlling a delay of said input clock signal based on a command from said shift register and for outputting a delayed input clock signal as said output clock signal to be compared by said phase detect circuit, said delay line having a delay state output; and a correction latch coupled to said control signal, said shift register and said delay state output, said correction latch generating an override shift command to said shift register when a state of minimum delay is provided by said delay state output.
Claim 2
Dependent Claim
177 words
A computer system comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop for synchronizing the required clock signals for said integrated circuits, said delay locked loop comprising: a phase detect circuit for comparing the phases of an input and output clock signal and for outputting a control signal based on said comparison; a delay line coupled to said input clock signal and a shift register, said delay line controlling a delay of said input clock signal based on a command from said shift register and for outputting a delayed input clock signal as said output clock signal to be compared by said phase detect circuit, said delay line having a delay state output; and a correction latch coupled to said control signal, said shift register and said delay state output, said correction latch generating an override shift command to said shift register when a state of minimum delay is provided by said delay state output.
Claim 3
Dependent Claim
45 words
A computer system as in claim 1, wherein said override shift command causes said shift register to output to said delay line a command to increase the delay in said delay line until the phase detect circuit generates a control signal to increase the delay.
Claim 4
Dependent Claim
49 words
A computer system as in claim 1, wherein said digital delay locked loop further comprises a reset mechanism coupled to said shift register for resetting said shift register to a predetermined state when contents of said shift register correspond to a state of maximum delay in said delay line.
Claim 5
Dependent Claim
61 words
A computer system as in claim 1, wherein said digital delay locked loop further comprises a divide by n frequency divider having an input coupled to said control signal and n outputs representing said control signal coupled to said correction latch, said n outputs controlling said correction latch to allow delay line correction on every nth input to said frequency divider.
Claim 6
Dependent Claim
11 words
A computer system as in claim 4, wherein n equals 2.
Claim 7
Dependent Claim
135 words
A computer system as in claim 1, wherein said delay line comprises at least two delay elements, at least one of which comprises: a first logic circuit coupled to said input clock signal and an N output stage of said shift register; a second logic circuit coupled to an output of said first logic circuit and an output of another of said at least two delay elements; and a third logic circuit coupled to an output of said second logic circuit and to an N+1 output stage of said shift register, whereby a transition from a low state to a high state between said N and N+1 output stages of said shift register controls an insertion point of said input clock signal into said delay line, thereby controlling said delay of said input clock signal.
Claim 8
Dependent Claim
17 words
A computer system as in claim 6, wherein each of said logic circuits is a NAND gate.
Claim 9
Dependent Claim
26 words
A computer system as in claim 7, wherein said at least one delay element ensures substantially symmetrical rising and falling edges of said output clock signal.
Claim 10
Dependent Claim
179 words
A computer system comprising: at least one printed circuit board having at least one reference clock and a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop for synchronizing the required clock signals for said integrated circuits, said delay locked loop comprising: a phase detect circuit for comparing the phases of an input and output signal and for outputting a control signal based on said comparison; a shift register responsive to said control signal; a delay line coupled to said input signal and said shift register, said delay line controlling a speed of said output signal based on a command from said shift register and for outputting said output signal to be compared by said phase detect circuit; and a reset mechanism coupled to a maximum delay stage of said shift register for resetting said shift register to a predetermined value when contents of said maximum delay stage correspond to a state of maximum delay in said delay line.
Claim 11
Dependent Claim
179 words
A computer system comprising: at least one printed circuit board having at least one reference clock and a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop for synchronizing the required clock signals for said integrated circuits, said delay locked loop comprising: a phase detect circuit for comparing the phases of an input and output signal and for outputting a control signal based on said comparison; a shift register responsive to said control signal; a delay line coupled to said input signal and said shift register, said delay line controlling a speed of said output signal based on a command from said shift register and for outputting said output signal to be compared by said phase detect circuit; and a reset mechanism coupled to a maximum delay stage of said shift register for resetting said shift register to a predetermined value when contents of said maximum delay stage correspond to a state of maximum delay in said delay line.
Claim 12
Dependent Claim
70 words
A computer system as in claim 9, wherein said digital delay locked loop further comprises: a latch circuit coupled to said shift register; and a divide by n frequency divider having an input coupled to said control signal and n outputs representing said control signal coupled to said latch circuit, said n outputs controlling said latch circuit to allow delay line correction on every nth input to said frequency divider.
Claim 13
Dependent Claim
11 words
A computer system as in claim 10, wherein n equals 2.
Claim 14
Dependent Claim
132 words
A computer system as in claim 9, wherein said delay line comprises at least two delay elements, at least one of which comprises: a first logic circuit coupled to said input signal and an N output stage of said shift register; a second logic circuit coupled to an output of said first logic circuit and an output of another of said at least two delay elements; and a third logic circuit coupled to an output of said second logic circuit and to an N+1 output stage of said shift register, whereby a transition from a low state to a high state between said N and N+1 output stages of said shift register controls an insertion point of said input signal into said delay line, thereby controlling said delay of said input signal.
Claim 15
Dependent Claim
17 words
A computer system as in claim 12, wherein each of said logic circuits is a NAND gate.
Claim 16
Dependent Claim
33 words
A computer system as in claim 13, wherein said at least one delay element ensures substantially symmetrical rising and falling edges of said output signal to be compared by said phase detect circuit.
Claim 17
Dependent Claim
160 words
A printed circuit board comprising: a plurality of integrated circuits, at least some of which require a clock signal; and at least one digital delay locked loop for synchronizing the required clock signals for said integrated circuits, said delay locked loop comprising: a phase detect circuit for comparing the phases of an input and output signal and for outputting a control signal based on said comparison; a delay line coupled to said input signal and a shift register, said delay line controlling a speed of said output signal based on a command from said shift register and for outputting said output signal to be compared by said phase detect circuit, said delay line having a delay state output; and a correction latch coupled to said control signal, said shift register and said delay state output, said correction latch generating an override shift command to said shift register when a state of minimum delay is provided by said delay state output.
Claim 18
Dependent Claim
160 words
A printed circuit board comprising: a plurality of integrated circuits, at least some of which require a clock signal; and at least one digital delay locked loop for synchronizing the required clock signals for said integrated circuits, said delay locked loop comprising: a phase detect circuit for comparing the phases of an input and output signal and for outputting a control signal based on said comparison; a delay line coupled to said input signal and a shift register, said delay line controlling a speed of said output signal based on a command from said shift register and for outputting said output signal to be compared by said phase detect circuit, said delay line having a delay state output; and a correction latch coupled to said control signal, said shift register and said delay state output, said correction latch generating an override shift command to said shift register when a state of minimum delay is provided by said delay state output.
Claim 19
Dependent Claim
46 words
A printed circuit board as in claim 15, wherein said override shift command causes said shift register to output to said delay line a command to increase the delay in said delay line until the phase detect circuit generates a control signal to increase the delay.
Claim 20
Dependent Claim
52 words
A printed circuit board as in claim 15, wherein said digital delay locked loop further comprises a reset mechanism coupled to a maximum delay stage of said shift register for resetting said shift register when contents of said maximum delay stage correspond to a state of maximum delay in said delay line.
Claim 21
Dependent Claim
62 words
A printed circuit board as in claim 15, wherein said digital delay locked loop further comprises a divide by n frequency divider having an input coupled to said control signal and n outputs representing said control signal coupled to said correction latch, said n outputs controlling said correction latch to allow delay line correction on every nth input to said frequency divider.
Claim 22
Dependent Claim
12 words
A printed circuit board as in claim 15, wherein n equals 2.
Claim 23
Dependent Claim
91 words
A printed circuit board as in claim 15, wherein said delay line comprises at least two delay elements, at least one of which comprises: a first logic circuit coupled to said input signal and an N output stage of said shift register; a second logic circuit coupled to an output of said first logic circuit and an output of another of said at least two delay elements; and a third logic circuit coupled to an output of said second logic circuit and to an N+1 output stage of said shift register.
Claim 24
Dependent Claim
18 words
A printed circuit board as in claim 20, wherein each of said logic circuits is a NAND gate.
Claim 25
Dependent Claim
34 words
A printed circuit board as in claim 21, wherein said at least one delay element ensures substantially symmetrical rising and falling edges of said output signal to be compared by said phase detect circuit.
Claim 26
Dependent Claim
155 words
A printed circuit board comprising: a plurality of integrated circuits, at least some of which require a clock signal; and at least one digital delay locked loop for synchronizing the required clock signals for said integrated circuits, said delay locked loop comprising: a phase detect circuit for comparing the phases of an input and output signal and for outputting a control signal used to control a shift register based on said comparison, a delay line coupled to said input signal and said shift register for controlling a speed of said output signal based on a command from said shift register and for outputting said output signal to be compared by said phase detect circuit; and a reset mechanism coupled to a maximum delay stage of said shift register for resetting said shift register to a predetermined state when contents of said maximum delay stage correspond to a state of maximum delay in said delay line.
Claim 27
Dependent Claim
155 words
A printed circuit board comprising: a plurality of integrated circuits, at least some of which require a clock signal; and at least one digital delay locked loop for synchronizing the required clock signals for said integrated circuits, said delay locked loop comprising: a phase detect circuit for comparing the phases of an input and output signal and for outputting a control signal used to control a shift register based on said comparison, a delay line coupled to said input signal and said shift register for controlling a speed of said output signal based on a command from said shift register and for outputting said output signal to be compared by said phase detect circuit; and a reset mechanism coupled to a maximum delay stage of said shift register for resetting said shift register to a predetermined state when contents of said maximum delay stage correspond to a state of maximum delay in said delay line.
Claim 28
Dependent Claim
71 words
A printed circuit board as in claim 23, wherein said digital delay locked loop further comprises: a latch circuit coupled to said shift register; and a divide by n frequency divider having an input coupled to said control signal and n outputs representing said control signal coupled to said latch circuit, said n outputs controlling said latch circuit to allow delay line correction on every nth input to said frequency divider.
Claim 29
Dependent Claim
12 words
A printed circuit board as in claim 24, wherein n equals 2.
Claim 30
Dependent Claim
133 words
A printed circuit board as in claim 23, wherein said delay line comprises at least two delay elements, at least one of which comprises: a first logic circuit coupled to said input signal and an N output stage of said shift register; a second logic circuit coupled to an output of said first logic circuit and an output of another of said at least two delay elements; and a third logic circuit coupled to an output of said second logic circuit and to an N+1 output stage of said shift register, whereby a transition from a low state to a high state between said N and N+1 output stages of said shift register controls an insertion point of said input signal into said delay line, thereby controlling said delay of said input signal.
Claim 31
Dependent Claim
18 words
A printed circuit board as in claim 26, wherein each of said logic circuits is a NAND gate.
Claim 32
Dependent Claim
34 words
A printed circuit board as in claim 27, wherein said at least one delay element ensures substantially symmetrical rising and falling edges of said output signal to be compared by said phase detect circuit.
Claim 33
Dependent Claim
130 words
A digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after the input signal, said delay line having a delay state output; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a phase detect signal related to the difference in phase between said two signals; a shift register connected to said delay line for controlling a delay of said delay line; and a correction latch coupled to the output of said phase detect circuit, said delay state output and said shift register, said correction latch sending an override signal to said shift register when a state of minimum delay is provided by said delay state output.
Claim 34
Dependent Claim
130 words
A digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after the input signal, said delay line having a delay state output; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a phase detect signal related to the difference in phase between said two signals; a shift register connected to said delay line for controlling a delay of said delay line; and a correction latch coupled to the output of said phase detect circuit, said delay state output and said shift register, said correction latch sending an override signal to said shift register when a state of minimum delay is provided by said delay state output.
Claim 35
Dependent Claim
45 words
A digital delay locked loop circuit as in claim 29, wherein said override shift command causes said shift register to output a command to increase the delay in said delay line until the phase detect circuit generates a phase detect signal to increase the delay.
Claim 36
Dependent Claim
46 words
A digital delay locked loop circuit as in claim 30, further comprising a reset mechanism coupled to said shift register for resetting said shift register to a predetermined state when contents of said shift register correspond to a state of maximum delay in said delay line.
Claim 37
Dependent Claim
64 words
A printed circuit board as in claim 29, wherein said digital delay locked loop further comprises a divide by n frequency divider having an input coupled to said phase detect signal and n outputs representing said phase detect signal coupled to said correction latch, said n outputs controlling said correction latch to allow delay line correction on every nth input to said frequency divider.
Claim 38
Dependent Claim
13 words
A digital delay locked loop as in claim 32, wherein n equals 2.
Claim 39
Dependent Claim
135 words
A digital delay locked loop as in claim 29, wherein said delay line comprises at least two delay elements, at least one of which comprises: a first logic circuit coupled to said input signal and an N output stage of said shift register; a second logic circuit coupled to an output of said first logic circuit and an output of another of said at least two delay elements; and a third logic circuit coupled to an output of said second logic circuit and to an N+1 output stage of said shift register, whereby a transition from a low state to a high state between said N and N+1 output stages of said shift register controls an insertion point of said input clock signal into said delay line, thereby controlling said delay of said input signal.
Claim 40
Dependent Claim
19 words
A digital delay locked loop as in claim 34, wherein each of said logic circuits is a NAND gate.
Claim 41
Dependent Claim
35 words
A digital delay locked loop as in claim 35, wherein said at least one delay element ensures substantially symmetrical rising and falling edges of said output signal to be compared by said phase detect circuit.
Claim 42
Dependent Claim
127 words
A digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after the input signal; a phase detect circuit for comparing the phases of the delayed output and input signals and generating a phase detect signal related to the difference in phase between said two signals; a shift register connected to said phase detect signal and said delay line for controlling a delay of said delay line proportional to said phase detect signal; and a reset mechanism coupled to a maximum delay stage of said shift register for resetting said shift register to a predetermined state when contents of said maximum delay stage correspond to a state of maximum delay in said delay line.
Claim 43
Dependent Claim
127 words
A digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after the input signal; a phase detect circuit for comparing the phases of the delayed output and input signals and generating a phase detect signal related to the difference in phase between said two signals; a shift register connected to said phase detect signal and said delay line for controlling a delay of said delay line proportional to said phase detect signal; and a reset mechanism coupled to a maximum delay stage of said shift register for resetting said shift register to a predetermined state when contents of said maximum delay stage correspond to a state of maximum delay in said delay line.
Claim 44
Dependent Claim
74 words
A digital delay locked loop as in claim 37, wherein said digital delay locked loop further comprises: a latch circuit coupled to said shift register; and a divide by n frequency divider having an input coupled to said phase detect signal and n outputs representing said phase detect signal coupled to said latch circuit, said n outputs controlling said latch circuit to allow delay line correction on every nth input to said frequency divider.
Claim 45
Dependent Claim
13 words
A digital delay locked loop as in claim 38, wherein n equals 2.
Claim 46
Dependent Claim
134 words
A digital delay locked loop as in claim 39, wherein said delay line comprises at least two delay elements, at least one of which comprises: a first logic circuit coupled to said input signal and an N output stage of said shift register; a second logic circuit coupled to an output of said first logic circuit and an output of another of said at least two delay elements; and a third logic circuit coupled to an output of said second logic circuit and to an N+1 output stage of said shift register, whereby a transition from a low state to a high state between said N and N+1 output stages of said shift register controls an insertion point of said input signal into said delay line, thereby controlling said delay of said input signal.
Claim 47
Dependent Claim
19 words
A digital delay locked loop as in claim 40, wherein each of said logic circuits is a NAND gate.
Claim 48
Dependent Claim
35 words
A digital delay locked loop as in claim 41, wherein said at least one delay element ensures substantially symmetrical rising and falling edges of said output signal to be compared by said phase detect circuit.
Claim 49
Independent Claim
170 words
A method of synchronizing the phases of an input signal and an output signal, the method comprising the steps of: receiving in a delay line an input signal and generating from the delay line a delayed output signal a predetermined time after the input signal; outputting a delay state output from the delay line to a correction circuit connected to the phase detect circuit; comparing the phases of the delayed output and input signals in a phase detect circuit and generating a phase detect signal related to the difference in phase between said output and input signals; applying the phase detect signal to a shift register connected to the delay line through the correction circuit; controlling a delay of the input signal in the delay line in accordance with a command from the shift register based on said phase detect signal; and applying an override shift command from the correction circuit to the shift register when the delay state output represents a state of minimum delay in said delay line.
Claim 50
Independent Claim
170 words
A method of synchronizing the phases of an input signal and an output signal, the method comprising the steps of: receiving in a delay line an input signal and generating from the delay line a delayed output signal a predetermined time after the input signal; outputting a delay state output from the delay line to a correction circuit connected to the phase detect circuit; comparing the phases of the delayed output and input signals in a phase detect circuit and generating a phase detect signal related to the difference in phase between said output and input signals; applying the phase detect signal to a shift register connected to the delay line through the correction circuit; controlling a delay of the input signal in the delay line in accordance with a command from the shift register based on said phase detect signal; and applying an override shift command from the correction circuit to the shift register when the delay state output represents a state of minimum delay in said delay line.
Claim 51
Dependent Claim
44 words
A method of synchronizing the phases of an input signal and an output signal as in claim 43, further comprising the step of: resetting said shift register when contents of said shift register correspond to a state of maximum delay in said delay line.
Claim 52
Dependent Claim
84 words
A method of synchronizing the phases of an input signal and an output signal as in claim 43, further comprising the step of: dividing the frequency of the output of said phase detect circuit in a frequency divider to generate a number of divided outputs representing the output of the phase detect circuit; and outputting the divided outputs to the correction circuit, whereby the divided outputs cause said correction circuit to provide said override shift command on every nth input to said frequency divider.
Claim 53
Dependent Claim
22 words
A method of synchronizing the phases of an input signal and an output signal as in claim 45, wherein n equals 2.
Claim 54
Dependent Claim
45 words
A method of synchronizing the phases of an input signal and an output signal as in claim 46, further comprising the step of: detecting when contents of a maximum delay stage in the shift register represents a state of maximum delay in said delay line.
Claim 55
Dependent Claim
144 words
A logic circuit delay element of a delay line coupled to a shift register for controlling a delay of an input signal in a digital delay locked loop circuit, said delay element comprising: a first logic circuit coupled to said input signal and an N output stage of said shift register; a second logic circuit coupled to an output of said first logic circuit and an output of another delay element of the digital delay lock loop circuit; and a third logic circuit coupled to an output of said second logic circuit and to an N+1 output stage of said shift register, whereby a transition from a low state to a high state between said N and N+1 output stages of said shift register controls an insertion point of said input signal into said delay line, thereby controlling said delay of said input signal.
Claim 56
Dependent Claim
144 words
A logic circuit delay element of a delay line coupled to a shift register for controlling a delay of an input signal in a digital delay locked loop circuit, said delay element comprising: a first logic circuit coupled to said input signal and an N output stage of said shift register; a second logic circuit coupled to an output of said first logic circuit and an output of another delay element of the digital delay lock loop circuit; and a third logic circuit coupled to an output of said second logic circuit and to an N+1 output stage of said shift register, whereby a transition from a low state to a high state between said N and N+1 output stages of said shift register controls an insertion point of said input signal into said delay line, thereby controlling said delay of said input signal.
Claim 57
Dependent Claim
17 words
A delay element as in claim 48, wherein each of said logic circuits is a NAND gate.
Claim 58
Dependent Claim
27 words
A delay element as in claim 49, wherein said NAND gates ensure substantially symmetrical rising and falling edges of an output signal representing a delayed input signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-30 | 2003-11-29 | 2004-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-30 | 2007-11-29 | 2008-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-30 | 2011-11-29 | 2012-05-30 | $7700.00 | Window Closed / Lapsed |