US6376299B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Capacitor for semiconductor memory device and method of manufacturing the same
Assignee: SK Hynix Inc
•
Filing: 2000-06-30
•
Granted: 2002-04-23
•
Expires: 2020-06-30
Abstract
Abstract Disclosed are a capacitor for a semiconductor memory device and a method of manufacturing the same. According to the present invention, the method includes the steps of: forming a lower electrode on a semiconductor substrate; nitride-treating the surface of the lower electrode so as to prevent a natural oxide layer from generating on the surface thereof; forming a Ta2O5 layer as a dielectric layer on the upper part of the lower electrode; forming a conductive barrier made of the silicon nitride layer on the upper part of the Ta2O5 layer; and forming an upper electrode on the upper part of the conductive barrier.
Inventors
- 👤 Kwang Chul Joo
- 👤 Kee Jeung Lee
- 👤 Il Keoun Han
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:24
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D1/682; H10D1/684; H10D1/711; H10D1/712; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6316; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/65; H10P14/6516; H10P14/6529; H10P14/6532; H10P14/6536; H10P14/6538; H10P14/6544; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69393; H10P14/694; H10P14/6943; H10P14/69433
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
63 words
A method of manufacturing a capacitor on a semiconductor substrate comprising the steps of: forming a lower electrode on the semiconductor substrate; nitride-treating the surface of the lower electrode; depositing the Ta 2 O 5 layer as the dielectric layer on the upper part of the surface nitride-treated lower electrode; and forming an upper electrode on the upper part of the dielectric layer.
Claim 2
Independent Claim
63 words
A method of manufacturing a capacitor on a semiconductor substrate comprising the steps of: forming a lower electrode on the semiconductor substrate; nitride-treating the surface of the lower electrode; depositing the Ta 2 O 5 layer as the dielectric layer on the upper part of the surface nitride-treated lower electrode; and forming an upper electrode on the upper part of the dielectric layer.
Claim 3
Dependent Claim
28 words
The method according to claim 1 , the Ta 2 O 5 layer is formed by surface-chemical-reacting Ta chemical vapor and O 2 gas inside a CVD chamber.
Claim 4
Dependent Claim
64 words
The method according to claim 1 , the Ta 2 O 5 layer is thermal-treated under an atmosphere of O 3 gas and UV-O 3 gas at a low temperature of 200 to 400° C. and at a high temperature of 750 to 950° C. between the formation step of the Ta 2 O 5 layer and the formation step of the upper electrode.
Claim 5
Dependent Claim
69 words
The method according to claim 1 , wherein the formation step of the Ta 2 O 5 layer further comprises the steps of: forming a first Ta 2 O 5 layer; first-thermal-treating the first Ta 2 O 5 layer; forming a second Ta 2 O 5 layer on the upper part of the thermal-treated first Ta 2 O 5 layer; and second-thermal-treating the second Ta 2 O 5 layer.
Claim 6
Dependent Claim
30 words
The method according to claim 4 , wherein the first thermal-treatment step or the second thermal-treatment step is N 2 O or O 2 plasma treatment or UV-O 3 treatment.
Claim 7
Dependent Claim
41 words
The method according to claim 1 , the surface nitride treatment of the lower electrode is performed in situ in a chamber maintaining a temperature of 200 to 700° C. and NH 3 or N 2 /H 2 plasma gas atmosphere.
Claim 8
Dependent Claim
46 words
The method according to claim 1 , further comprising a step of forming a conductive barrier made of the silicon nitride layer on the upper part thereof, between the formation step of the Ta 2 O 5 layer and the formation step of the upper electrode.
Claim 9
Dependent Claim
29 words
The method according to claim 7 , wherein the conductive barrier is formed under an atmosphere of plasma gas containing nitrogen at a temperature of 200 to 400° C.
Claim 10
Dependent Claim
32 words
The method according to claim 7 , wherein the conductive barrier is formed in a furnace having an atmosphere of gas containing nitrogen components at a temperature of 750 to 950° C.
Claim 11
Dependent Claim
31 words
The method according to claim 7 , wherein the conductive barrier is formed by RTN under an atmosphere of gas containing nitrogen components at a temperature of 750 to 950° C.
Claim 12
Independent Claim
96 words
A method of manufacturing a capacitor on a semiconductor substrate comprising the steps of: forming a lower electrode on the semiconductor substrate; nitride-treating the surface of the lower electrode so as to prevent a natural oxide layer from generating on the surface thereof; forming a Ta 2 O 5 layer as a dielectric layer on the upper part of the lower electrode; forming a conductive barrier made of the silicon nitride layer on the upper part of the Ta 2 O 5 layer; and forming an upper electrode on the upper part of the conductive barrier.
Claim 13
Independent Claim
96 words
A method of manufacturing a capacitor on a semiconductor substrate comprising the steps of: forming a lower electrode on the semiconductor substrate; nitride-treating the surface of the lower electrode so as to prevent a natural oxide layer from generating on the surface thereof; forming a Ta 2 O 5 layer as a dielectric layer on the upper part of the lower electrode; forming a conductive barrier made of the silicon nitride layer on the upper part of the Ta 2 O 5 layer; and forming an upper electrode on the upper part of the conductive barrier.
Claim 14
Dependent Claim
29 words
The method according to claim 11 , wherein the Ta 2 O 5 layer is formed by surface-chemical-treating Ta chemical vapor and O 2 gas in a CVD chamber.
Claim 15
Dependent Claim
65 words
The method according to claim 11 , wherein the Ta 2 O 5 layer is thermal-treated under an atmosphere of O 3 gas and UV-O 3 gas at a low temperature of 200 to 400° C. and at a high temperature of 750 to 950° C. between the formation step of the Ta 2 O 5 layer and the formation step of the conductive barrier.
Claim 16
Dependent Claim
68 words
The method according to claim 11 , wherein the formation step of the Ta 2 O 5 layer comprises the steps of: forming a first Ta 2 O 5 layer; first-thermal-treating the first Ta 2 O 5 layer; forming a second Ta 2 O 5 layer on the upper part of the thermal-treated first Ta 2 O 5 layer; and second-thermal-treating the second Ta 2 O 5 layer.
Claim 17
Dependent Claim
30 words
The method according to claim 14 , wherein the first thermal-treatment step or the second thermal-treatment step is N 2 O or O 2 plasma treatment or UV-O 3 treatment.
Claim 18
Dependent Claim
43 words
The method according to claim 11 , wherein the surface nitride treatment of the lower electrode is performed in situ in a chamber maintaining atmosphere of NH 3 or N 2 /H 2 plasma gas at a temperature of 200 to 700° C.
Claim 19
Dependent Claim
31 words
The method according to claim 11 , wherein the conductive barrier is formed by a plasma treatment at temperature range of 200 to 400° C. by using a gas containing nitrogen.
Claim 20
Dependent Claim
33 words
The method according to claim 11 , wherein the conductive barrier is formed inside a furnace having an atmosphere of gas containing nitrogen components in a temperature range of 750 to 950° C.
Claim 21
Dependent Claim
31 words
The method according to claim 11 , wherein the conductive barrier is formed by RTN under an atmosphere of gas containing nitrogen components at a temperature of 750 to 950° C.
Claim 22
Dependent Claim
48 words
The method according to claim 11 , wherein in the thermal Ta 2 O 5 layer is thermal-treated under an atmosphere of O 3 gas and UV-O 3 gas at a low temperature of 200 to 400° C. and at a high temperature of 750 to 950° C.
Claim 23
Independent Claim
192 words
A method of manufacturing a capacitor on a semiconductor substrate comprising the steps of: forming a lower electrode on the semiconductor substrate; nitride-treating the surface of the lower electrode inside a chamber maintaining NH 3 or N 2 /H 2 plasma gas and a temperature of 200 to 700° C. so as to prevent a natural oxide layer from generating on the surface thereof; forming a Ta 2 O 5 layer as a dielectric layer on the upper part of the lower electrode; crystallizing the Ta 2 O 5 layer after thermal-treatment thereof; forming a conductive barrier made of the silicon nitride layer on the upper part of the Ta 2 O 5 layer in a chamber maintaining plasma gas containing nitrogen and a temperature of 200 to 400° C.; and forming an upper electrode on the upper part of the conductive barrier, wherein the surface nitride treatment step of the lower electrode, the formation step of the Ta 2 O 5 layer, the thermal-treating and then crystallizing step of the Ta 2 O 5 layer and the formation step of the conductive barrier are performed in situ in the same chamber.
Claim 24
Independent Claim
192 words
A method of manufacturing a capacitor on a semiconductor substrate comprising the steps of: forming a lower electrode on the semiconductor substrate; nitride-treating the surface of the lower electrode inside a chamber maintaining NH 3 or N 2 /H 2 plasma gas and a temperature of 200 to 700° C. so as to prevent a natural oxide layer from generating on the surface thereof; forming a Ta 2 O 5 layer as a dielectric layer on the upper part of the lower electrode; crystallizing the Ta 2 O 5 layer after thermal-treatment thereof; forming a conductive barrier made of the silicon nitride layer on the upper part of the Ta 2 O 5 layer in a chamber maintaining plasma gas containing nitrogen and a temperature of 200 to 400° C.; and forming an upper electrode on the upper part of the conductive barrier, wherein the surface nitride treatment step of the lower electrode, the formation step of the Ta 2 O 5 layer, the thermal-treating and then crystallizing step of the Ta 2 O 5 layer and the formation step of the conductive barrier are performed in situ in the same chamber.
Claim 25
Dependent Claim
29 words
The method according to claim 21 , wherein the Ta 2 O 5 layer is formed by surface-chemical-reacting Ta chemical vapor and O 2 gas inside a CVD chamber.
Claim 26
Dependent Claim
68 words
The method according to claim 21 , wherein the formation step of the Ta 2 O 5 layer comprises the steps of: forming a first Ta 2 O 5 layer; first-thermal-treating the first Ta 2 O 5 layer; forming a second Ta 2 O 5 layer on the upper part of the thermal-treated first Ta 2 O 5 layer; and second-thermal-treating the second Ta 2 O 5 layer.
Claim 27
Dependent Claim
28 words
The method according to claim 23 , wherein the first-thermal-treatment step or the second-thermal-treatment step is N 2 O or O 2 plasma treatment or UV-O 3 treatment.
References Cited (Backward Citations)
US4130694A
Cited
EP0046868A2
Cited
JPS62136035A
Cited
JPS6338248A
Cited
JPH01173622A
Cited
JPH02226754A
Cited
JPH05167008A
Cited
JPH05335483A
Cited
US5438012A
Cited
US5444006A
Cited
JPH06163819A
Cited
US5352623A
Cited
JPH0714993A
Cited
JPH0745467A
Cited
US5452178A
Cited
US5741721A
Cited
US5362632A
Cited
US5753945A
Cited
US5859760A
Cited
US5763300A
Cited
US5786248A
Cited
US5631188A
Cited
US5981331A
Cited
GB2320131A
Cited
US5939131A
Cited
US5872415A
Cited
US5776660A
Cited
US5980977A
Cited
US6150183A
Cited
US5936831A
Cited
US5977582A
Cited
GB2326279A
Cited
EP0900859A2
Cited
US5910880A
Cited
US5837576A
Cited
WO1999033098A1
Cited
JPH11191612A
Cited
JPH11233723A
Cited
GB2344218A
Cited
GB2347787A
Cited
US6207489B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-04-22 | 2005-10-22 | 2006-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-04-22 | 2009-10-22 | 2010-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-04-22 | 2013-10-22 | 2014-04-23 | $7700.00 | Window Closed / Lapsed |