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US5837576A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for forming a capacitor using a silicon oxynitride etching stop layer

Assignee: Vanguard International Semiconductor Corp
•
Filing: 1997-10-31
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Granted: 1998-11-17
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Expires: 2017-10-31
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Abstract

Abstract A polysilicon layer is deposited on a dielectric layer. A silicon oxynitride layer is then formed on the polysilicon layer. A photoresist is imprinted with a pattern on the silicon oxynitride layer to define the storage node. An etching step is used to etch the silicon oxynitride layer and the polysilicon layer to formed the storage node. A HSG silicon is deposited on the silicon oxynitride layer and on the side walls of the storage node. An isotropically etching step is performed to remove the HSG layer on the top of the storage node. The silicon oxynitride is then removed. A dielectric layer is then formed along the surface of the storage node. A conductive layer is deposited over the dielectric layer. The conductive layer is used as the top storage node.

Inventors

  • 👤 Li-Yeat Chen
  • 👤 Jin-Dong Chen
  • 👤 Erik S. Jeng
  • 👤 Ing-Ruey Liaw

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 07:34
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 145 words
A method of manufacturing a capacitor, comprising the steps of: forming a silicon layer; forming a silicon oxynitride layer on said silicon layer to serve as an etching stop layer and a bottom anti reflective bottom coating; patterning said silicon layer and said silicon oxynitride layer to define a first storage node for said capacitor; forming a hemispherical grained (HSG) silicon on side walls of said first storage node and on said silicon oxynitride layer; removing said HSG silicon on said silicon oxynitride layer; removing said silicon oxynitride layer and a portion of said HSG layer remaining on said side walls of said first storage node; forming a dielectric layer along a surface of said first storage node and on said portion of said HSG layer; and forming a conductive layer over said dielectric layer to serve as a second storage node of said capacitor.
Claim 2
Independent Claim 145 words
A method of manufacturing a capacitor, comprising the steps of: forming a silicon layer; forming a silicon oxynitride layer on said silicon layer to serve as an etching stop layer and a bottom anti reflective bottom coating; patterning said silicon layer and said silicon oxynitride layer to define a first storage node for said capacitor; forming a hemispherical grained (HSG) silicon on side walls of said first storage node and on said silicon oxynitride layer; removing said HSG silicon on said silicon oxynitride layer; removing said silicon oxynitride layer and a portion of said HSG layer remaining on said side walls of said first storage node; forming a dielectric layer along a surface of said first storage node and on said portion of said HSG layer; and forming a conductive layer over said dielectric layer to serve as a second storage node of said capacitor.
Claim 3
Dependent Claim 16 words
The method of claim 1, wherein said silicon oxynitride layer has a thickness about 200-1000 angstroms.
Claim 4
Dependent Claim 20 words
The method of claim 1, wherein said HSG silicon on said silicon oxynitride layer is removed by an anisotropically etching.
Claim 5
Dependent Claim 20 words
The method of claim 1, wherein said dielectric layer is formed of a tantalum oxide (Ta 2 O 5 ).
Claim 6
Dependent Claim 17 words
The method of claim 1, wherein said dielectric layer is formed of a triple film of oxide/nitride/oxide.
Claim 7
Dependent Claim 18 words
The method of claim 1, wherein said dielectric film is formed of a double film of nitride/oxide film.
Claim 8
Dependent Claim 21 words
The method of claim 1, wherein said silicon layer comprises a doped amorphous silicon, a doped polysilicon, an in-situ doped polysilicon.
Claim 9
Dependent Claim 18 words
The method of claim 1, wherein said conductive layer comprises a doped polysilicon and an in-situ doped polysilicon.

References Cited (Backward Citations)

US5554557A Cited
US5618747A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-11-16 2002-05-18 2002-11-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-11-16 2006-05-18 2006-11-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-11-16 2010-05-18 2010-11-17 $7700.00 Window Closed / Lapsed

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