Patent US6142683A successfully refreshed from Google Patents.
US6142683A
Expired / Lapsed
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Debug interface including data steering between a processor, an input/output port, and a trace logic
Assignee: Advanced Micro Devices Inc
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Filing: 1998-03-04
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Granted: 2000-11-07
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Expires: 2018-03-04
Abstract
Abstract A system for debugging a processor includes a data steering circuit for steering commands and data from a debug port and a parallel input/output port. The data steering circuit also directs commands and data to from the debug port and the parallel input/output port to the same set of debug registers. The data steering circuit also selectively directs trace information indicative of execution of instructions in the processor to either a trace buffer or directly out to a port, such as the debug port or the parallel input/output port.
Inventors
- 👤 Venkateswara Rao Madduri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:23
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/3698; G06F11/30; G06F11/34; G06F11/3466; G06F11/348; G06F11/362; G06F11/3632; G06F11/3636; G06F11/3648; G06F11/3656; G06F11/22; G06F11/26; G06F11/261; G06F11/3409; G06F11/3419; G06F11/3423; G06F2201/00; G06F2201/86
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
127 words
A processor comprising: a processor core within the processor and responsive to instructions to perform processing operations; a parallel input/output port coupled to the processor core and communicating information between an external device and the processor core; a debug port coupled to the processor core and communicating debug information between a debug device and the processor; a common decode logic coupled to the processor core, the parallel input/output port, and the debug port for decoding commands from the parallel input/output port and the debug port; and a data steering logic coupled to the processor core, the parallel input/output port, and the debug port, the data steering logic selectively steering commands and data from either the parallel input/output port or the debug port to the common decode logic.
Claim 2
Dependent Claim
127 words
A processor comprising: a processor core within the processor and responsive to instructions to perform processing operations; a parallel input/output port coupled to the processor core and communicating information between an external device and the processor core; a debug port coupled to the processor core and communicating debug information between a debug device and the processor; a common decode logic coupled to the processor core, the parallel input/output port, and the debug port for decoding commands from the parallel input/output port and the debug port; and a data steering logic coupled to the processor core, the parallel input/output port, and the debug port, the data steering logic selectively steering commands and data from either the parallel input/output port or the debug port to the common decode logic.
Claim 3
Dependent Claim
69 words
A processor according to claim 1 further comprising: a plurality of registers coupled to the parallel input/output port and the debug port for holding data and commands from the parallel input/output port and the debug port, wherein the data steering logic selectively steers commands and data from either the parallel input/output port or the debug port to the plurality of registers for usage with respect to the processor core.
Claim 4
Dependent Claim
15 words
A processor according to claim 1 wherein the debug port is a parallel debug port.
Claim 5
Dependent Claim
15 words
A processor according to claim 1 wherein the debug port is a serial debug port.
Claim 6
Dependent Claim
19 words
A processor according to claim 1 wherein the debug port is a JTAG (Joint Test Action Group) standard port.
Claim 7
Dependent Claim
69 words
A processor according to claim 1, further comprising: a trace logic accessing trace information indicating instruction execution flow in the processor core; a trace buffer coupled to the trace logic for selectively receiving the trace information; a trace port coupled to the trace logic for selectively communicating the trace information, wherein the data steering logic selectively directs the trace information to either the trace buffer or the trace port.
Claim 8
Dependent Claim
14 words
A processor according to claim 1, wherein the debug device is a host system.
Claim 9
Dependent Claim
14 words
An integrated computer chip comprising: the processor according to claim 1; and a storage.
Claim 10
Dependent Claim
62 words
A debug interface for interfacing a processor to a debug device, the debug interface comprising: an input/output port; a buffer coupled to the processor; a data steering controller coupled to the processor, the input/output port, and the buffer, the data steering controller directing data from the processor to either the input/output port or the buffer depending on the content of the buffer.
Claim 11
Dependent Claim
62 words
A debug interface for interfacing a processor to a debug device, the debug interface comprising: an input/output port; a buffer coupled to the processor; a data steering controller coupled to the processor, the input/output port, and the buffer, the data steering controller directing data from the processor to either the input/output port or the buffer depending on the content of the buffer.
Claim 12
Dependent Claim
28 words
A debug interface according to claim 9, wherein: the data steering controller determines a destination of the directed data without operation of instructions executed by processor native code.
Claim 13
Dependent Claim
40 words
A debug interface according to claim 9, wherein: the data steering controller fetches data from a storage coupled to the processor, writes the fetched data to a destination selected between the input/output port and the buffer, increments a data counter.
Claim 14
Dependent Claim
16 words
A debug interface according to claim 9 wherein the input/output port is a serial debug port.
Claim 15
Dependent Claim
20 words
A debug interface according to claim 9 wherein the input/output port is a JTAG (Joint Test Action Group) standard port.
Claim 16
Dependent Claim
15 words
A debug interface according to claim 9, wherein the debug device is a host system.
Claim 17
Dependent Claim
19 words
An integrated computer chip comprising: the processor; and the debug interface according to claim 9 coupled to the processor.
Claim 18
Dependent Claim
149 words
A debug interface for interfacing a processor to an external debug device, the debug interface comprising: a debug port coupled to the processor and including a plurality of pins for communicating signals with the external debug device; a parallel input/output port coupled to the processor and including a plurality of pins for communicating signals with the external debug device; a decode logic coupled to the debug port and the parallel input/output port, the decode logic for decoding debug commands and data received both from the debug port and the parallel input/output port; and a data steering controller coupled to the debug port, the parallel input/output port, and the decode logic, the data steering controller including a debug port state machine and a parallel port state machine, the data steering controller selectively directing data between the processor and the debug port, and between the processor and the parallel input/output port.
Claim 19
Dependent Claim
149 words
A debug interface for interfacing a processor to an external debug device, the debug interface comprising: a debug port coupled to the processor and including a plurality of pins for communicating signals with the external debug device; a parallel input/output port coupled to the processor and including a plurality of pins for communicating signals with the external debug device; a decode logic coupled to the debug port and the parallel input/output port, the decode logic for decoding debug commands and data received both from the debug port and the parallel input/output port; and a data steering controller coupled to the debug port, the parallel input/output port, and the decode logic, the data steering controller including a debug port state machine and a parallel port state machine, the data steering controller selectively directing data between the processor and the debug port, and between the processor and the parallel input/output port.
Claim 20
Dependent Claim
69 words
A debug interface according to claim 16 further comprising: a register coupled to the parallel input/output port and coupled to the debug port for holding data and commands from the parallel input/output port and the debug port, wherein the data steering controller selectively steers commands and data from either the parallel input/output port or the debug port to the plurality of registers for usage with respect to the processor.
Claim 21
Dependent Claim
16 words
A debug interface according to claim 16 wherein the debug port is a parallel debug port.
Claim 22
Dependent Claim
16 words
A debug interface according to claim 16 wherein the debug port is a serial debug port.
Claim 23
Dependent Claim
20 words
A debug interface according to claim 16 wherein the debug port is a JTAG (Joint Test Action Group) standard port.
Claim 24
Dependent Claim
30 words
A debug interface according to claim 16 wherein the parallel port state machine includes a logic for enabling the parallel input/output port to output trace records generated by processor execution.
Claim 25
Dependent Claim
15 words
A debug interface according to claim 16 wherein the debug device is a host system.
Claim 26
Dependent Claim
15 words
An integrated computer chip comprising: the processor; and the debug interface according to claim 16.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-07 | 2004-05-08 | 2004-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-07 | 2008-05-08 | 2008-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-07 | 2012-05-08 | 2012-11-07 | $7700.00 | Window Closed / Lapsed |