US6067648A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable pulse generator
Assignee: NEOSEM Inc
•
Filing: 1998-03-02
•
Granted: 2000-05-23
•
Expires: 2018-03-02
Abstract
Abstract A digital programmable delay which provides a series of pulses that are programmed in both pulse latency and trigger latency to control the operation of a memory module test system.
Inventors
- 👤 Paul R. Hunter
- 👤 Archer R. Lawrence
- 👤 Jack C. Little
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:38
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1502; G; G11; G11C; G11C29/00; G11C29/56; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31921
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
219 words
A programmable pulse generator for generating a pulse signal to gate control, address, and data signals of a memory test system having a microprocessor, which comprises: a configuration register in electrical communication with said microprocessor and having stored therein a trigger latency code and a pulse latency code, and a mode bit received from said microprocessor; a leading delay cell in electrical communication with said configuration register and said microprocessor, and receiving said trigger latency code and said pulse latency code from said configuration register, and a trigger signal and a latency value from said microprocessor for generating a leading edge signal for said pulse signal; trailing delay cell in electrical communication with said configuration register, said microprocessor, and said leading delay cell, and receiving said trigger latency code and said pulse latency code from said configuration register, and said trigger signal and said latency value from said microprocessor for generating a trailing edge signal for said pulse signal; and a pulse controller in electrical communication with said configuration register, said leading delay cell, and said trailing delay cell, and receiving said mode bit signal from said configuration register to select between combining said leading edge signal and said trailing edge signal to form said pulse signal, and issuing said leading edge signal and said trailing edge signal independently.
Claim 2
Dependent Claim
219 words
A programmable pulse generator for generating a pulse signal to gate control, address, and data signals of a memory test system having a microprocessor, which comprises: a configuration register in electrical communication with said microprocessor and having stored therein a trigger latency code and a pulse latency code, and a mode bit received from said microprocessor; a leading delay cell in electrical communication with said configuration register and said microprocessor, and receiving said trigger latency code and said pulse latency code from said configuration register, and a trigger signal and a latency value from said microprocessor for generating a leading edge signal for said pulse signal; trailing delay cell in electrical communication with said configuration register, said microprocessor, and said leading delay cell, and receiving said trigger latency code and said pulse latency code from said configuration register, and said trigger signal and said latency value from said microprocessor for generating a trailing edge signal for said pulse signal; and a pulse controller in electrical communication with said configuration register, said leading delay cell, and said trailing delay cell, and receiving said mode bit signal from said configuration register to select between combining said leading edge signal and said trailing edge signal to form said pulse signal, and issuing said leading edge signal and said trailing edge signal independently.
Claim 3
Dependent Claim
74 words
The programmable pulse generator of claim 1, wherein said leading delay cell and said trailing delay cell each have a pulse latency delay pipeline and a trigger delay pipeline, and said pulse latency delay pipeline and said trigger delay pipeline respectively are programmable in latency in response to said pulse latency code and said trigger latency code, and said pulse latency delay pipeline further is programmable in latency in response to said latency value.
Claim 4
Dependent Claim
85 words
The programmable pulse generator of claim 2, wherein said leading delay cell and said trailing delay cell each have a programmable delay chain in electrical communication with said pulse latency delay pipeline and said trigger delay pipeline, for receiving said latency value from said pulse latency delay pipeline upon receipt of said trigger signal from said trigger delay pipeline, and for imparting a programmable delay to said latency value in the range of 0 to 63.5 nanoseconds and with a typical resolution of 0.5 nanoseconds.
Claim 5
Dependent Claim
92 words
The programmable pulse generator of claim 3, wherein said programmable pulse generator includes a system clock generator, and a JTAG interface in electrical communication with said microprocessor and said configuration register, and said pulse latency delay pipeline includes a facility for receiving a delay value from said JTAG interface which is synchronized with a JTAG clock signal issued by said JTAG interface, and for loading said delay value into a first stage of said pulse latency delay pipeline which is synchronized with a system clock signal issued by said system clock generator.
Claim 6
Dependent Claim
109 words
The programmable pulse generator of claim 1, wherein said pulse controller is comprised of a state machine in electrical communication with said configuration register, said leading delay cell, said trailing delay cell, and said microprocessor, and receiving said leading edge signal and said trailing edge signal for forming said pulse signal, and generating a leading delay cell reset signal and a trailing delay cell reset signal for clearing said leading delay cell and said trailing delay cell to await receipt of a new pulse latency code and a new trigger latency code from said configuration register, and a new trigger signal and a new latency value from said microprocessor.
Claim 7
Dependent Claim
93 words
The programmable pulse generator of claim 5, wherein said pulse controller is further comprised of a multiplexer means in electrical communication with said configuration register, said trailing edge cell, and said leading edge cell, and receiving said pulse signal from said state machine, and said leading edge signal and said trailing edge signal respectively from said leading edge cell and said trailing edge cell, and responsive to said mode bit signal for selecting among said pulse signal, said leading edge signal, and said trailing, edge signal for output to said memory test system.
Claim 8
Dependent Claim
41 words
The programmable pulse generator of claim 5, wherein said state machine recognizes an arrival of said trailing edge signal before said leading edge signal, and in response thereto suppresses generation of a spurious output pulse, and returns to a quiescent state.
Claim 9
Independent Claim
186 words
A method of controlling latency in generating a pulse signal to a memory system having a microprocessor; comprising the steps of: generating a first trigger signal; selecting between a pulse generation mode, and a leading trigger edge and a trailing trigger edge flow-through mode; selecting a trigger latency code to control latency of said first trigger signal; generating a second trigger signal having a latency in accordance with said trigger latency code; selecting a pulse latency code to control latency of a first latency value received from said microprocessor; generating a second latency value having a latency in accordance with said pulse latency code; in response to said second trigger signal, generating a leading edge signal and a trailing edge signal which are delayed in accordance with said second latency value; if said pulse generation mode has been selected, generating a pulse which is defined by said leading edge signal and said trailing edge signal; and if said leading trigger edge and said trailing trigger edge flow-through mode has been selected, passing said leading edge signal and said trailing edge signal to said memory test system.
Claim 10
Independent Claim
186 words
A method of controlling latency in generating a pulse signal to a memory system having a microprocessor; comprising the steps of: generating a first trigger signal; selecting between a pulse generation mode, and a leading trigger edge and a trailing trigger edge flow-through mode; selecting a trigger latency code to control latency of said first trigger signal; generating a second trigger signal having a latency in accordance with said trigger latency code; selecting a pulse latency code to control latency of a first latency value received from said microprocessor; generating a second latency value having a latency in accordance with said pulse latency code; in response to said second trigger signal, generating a leading edge signal and a trailing edge signal which are delayed in accordance with said second latency value; if said pulse generation mode has been selected, generating a pulse which is defined by said leading edge signal and said trailing edge signal; and if said leading trigger edge and said trailing trigger edge flow-through mode has been selected, passing said leading edge signal and said trailing edge signal to said memory test system.
References Cited (Backward Citations)
US3162815A
Cited
US3840815A
Cited
US3976940A
Cited
US4165490A
Cited
US4464581A
Cited
US4415861A
Cited
US4550307A
Cited
US4494021A
Cited
US4490821A
Cited
US4637018A
Cited
US4797585A
Cited
US5640547A
Cited
US4755704A
Cited
US5122679A
Cited
US4868522A
Cited
US5028824A
Cited
US5008563A
Cited
US5418932A
Cited
US5293626A
Cited
US5208598A
Cited
US5224129A
Cited
US5306959A
Cited
US5309034A
Cited
US5144255A
Cited
US5307381A
Cited
US5313108A
Cited
US5485490A
Cited
US5446867A
Cited
US5298866A
Cited
US5481573A
Cited
US5610546A
Cited
US5422585A
Cited
US5559477A
Cited
US5568075A
Cited
US5554946A
Cited
US5631596A
Cited
US5570053A
Cited
US5594376A
Cited
US5486783A
Cited
US5638016A
Cited
US5570045A
Cited
US5642067A
Cited
US5781049A
Cited
US5686846A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-23 | 2003-11-22 | 2004-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-23 | 2007-11-22 | 2008-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-23 | 2011-11-22 | 2012-05-23 | $7700.00 | Window Closed / Lapsed |