Method and apparatus for providing clock de-skewing on an integrated circuit board

Claim 2

An integrated circuit having circuitry to compensate for signal delays therein, said integrated circuit comprises: a) a first input buffering means for receiving and buffering a clocked input reference signal, wherein said input buffer means generates a first signal delay upon said input reference signal; b) signal regulating means coupled to said input buffering means for generating a synchronizing signal delay to said input reference signal for synchronizing an output data signal with said input reference signal, said signal regulating means having an output port and at least one input port and a feedback loop coupling said output port to said at least one input port; c) a first output latching means coupled to said output port of said signal regulating means at a first input of said output latching means for latching said output data signal, wherein said output latching means generates a second signal delay upon said output data signal; d) a first output buffering means coupled to said output latching means for buffering said output data signal, wherein said output buffering means generates a third signal delay upon said output data signal; and simulated signal delay means coupled in said feedback loop for generating a delayed input signal to said signal regulating means, said delayed input signal having a generated simulated signal delay approximately equal to said first signal delay of said input buffering means, said second signal delay of said output latching means and said third signal delay of said output buffering means, wherein said delayed input signal is operative to enable said signal regulating means to provide a signal delay to said input reference signal so as to synchronize said input reference signal with said output data signal.

Claim 3

An integrated circuit as recited in claim 1, wherein said simulated signal delay means includes a second input buffering means, a second output latching means and a second output buffering means.

Claim 4

An integrated circuit as recited in claim 2, wherein said signal regulating means includes: (i) phase detecting means for measuring the respective signal phases between an output signal of said input buffering means and said delayed input signal of said simulated signal delay means; and (ii) regulated delay means coupled to said phase detecting means for generating said synchronizing signal delay responsive to the measured signal phase difference between said output signal of said input buffering means and said delayed input signal of said simulated signal delay means.

Claim 5

An integrated circuit as recited in claim 1, further including: g) an asynchronous logic device coupled to a second input of said output latching means for providing a data input signal to said output latching means.

Claim 6

An integrated circuit as recited in claim 4, further including: h) a plurality of synchronous logic devices coupled to a corresponding plurality of inputs of said asynchronous logic device for providing dam input to said asynchronous logic device.

Claim 7

An integrated circuit as recited in claim 5, further including: (i) clock driving means coupled to said regulating means for driving said input reference signal to said plurality of synchronous logic devices.

Claim 8

An integrated circuit as recited in claim 6, wherein each of said plurality of synchronous logic devices is a flip-flop device.

Claim 9

A circuit board having a plurality of integrated circuits provided thereon, wherein each of said plurality of integrated circuits receives a common clock input reference signal and provides an output data signal therefrom, and includes compensating circuitry for synchronizing said output data signal with said input reference signal, said compensating circuitry comprises: a) a first input buffering means for receiving and buffering said common clock input reference signal, wherein said input buffer means generates a first signal delay upon said input reference signal; b) signal regulating means coupled to said input buffering means for providing a synchronizing signal delay to said input reference signal for synchronizing said output signal with said input reference signal, said signal regulating means having an output port and at least one input port and a feedback loop coupling said output port to said at least one input port; c) clock driving means coupled to said signal regulating means for driving said input reference signal to a plurality of logic devices; d) a first output latching means coupled to said clock driving means at a first input of said output latching means for latching said output signal, wherein said output latching means generates a second signal delay upon said output signal; e) a first output buffering means coupled to said output latching means for buffering said output data signal, wherein said output buffering means generates a third signal delay upon said output data signal; f) asynchronous logic means coupled to a second input of said output latch for providing a data input thereto, wherein said asynchronous logic means has a plurality of inputs respectively coupled to said plurality of logic devices; and g) simulated signal delay means coupled in said feedback loop for generating a delayed input signal to said signal regulating means, said delayed input signal having a generated simulated signal delay approximately equal to said first signal delay of said input buffering means, said second signal delay of said output latching means and said third signal delay of said buffering means, wherein said delayed input signal of operative to enable said signal regulating means to provide a signal delay to said input reference signal so as to synchronize said input reference signal with said output dam signal.

Claim 10

A circuit board having a plurality of integrated circuits provided thereon, wherein each of said plurality of integrated circuits receives a common clock input reference signal and provides an output data signal therefrom, and includes compensating circuitry for synchronizing said output data signal with said input reference signal, said compensating circuitry comprises: a) a first input buffering means for receiving and buffering said common clock input reference signal, wherein said input buffer means generates a first signal delay upon said input reference signal; b) signal regulating means coupled to said input buffering means for providing a synchronizing signal delay to said input reference signal for synchronizing said output signal with said input reference signal, said signal regulating means having an output port and at least one input port and a feedback loop coupling said output port to said at least one input port; c) clock driving means coupled to said signal regulating means for driving said input reference signal to a plurality of logic devices; d) a first output latching means coupled to said clock driving means at a first input of said output latching means for latching said output signal, wherein said output latching means generates a second signal delay upon said output signal; e) a first output buffering means coupled to said output latching means for buffering said output data signal, wherein said output buffering means generates a third signal delay upon said output data signal; f) asynchronous logic means coupled to a second input of said output latch for providing a data input thereto, wherein said asynchronous logic means has a plurality of inputs respectively coupled to said plurality of logic devices; and g) simulated signal delay means coupled in said feedback loop for generating a delayed input signal to said signal regulating means, said delayed input signal having a generated simulated signal delay approximately equal to said first signal delay of said input buffering means, said second signal delay of said output latching means and said third signal delay of said buffering means, wherein said delayed input signal of operative to enable said signal regulating means to provide a signal delay to said input reference signal so as to synchronize said input reference signal with said output dam signal.

Claim 11

A circuit board as recited in claim 8, wherein said simulated signal delay means includes a second input buffering means, a second output latching means and a second output buffering means.

Claim 12

A circuit board as recited in claim 8, wherein said signal regulating means includes: (i) phase detecting means for measuring the respective signal phases between an output signal of said input buffering means and said delayed input signal of said simulated signal delay means; and (ii) regulated delay means coupled to said phase detecting means for generating said synchronizing signal delay responsive to the measured signal phase difference between said output signal of said input buffering means and said delayed input signal of said simulated signal delay means.

Claim 13

A circuit board as recited in claim 10, wherein each of said plurality of logic devices is a flip-flop device.

Claim 16

A method of maintaining signal synchronization in an integrated circuit as recited in claim 12, further including the steps of; h) driving said input reference signal to a plurality of logic devices; i) inputting a plurality of data signals to said plurality of logic devices; and j) inputting a plurality of data signals from said plurality of logic devices to an asynchronous logic device; and k) latching said output data signal with a data signal from said asynchronous logic device in reference to said input reference signal.