Integrated logic circuit with clock skew adjusters

Claim 2

An integrated logical circuit, comprising: clock means for feeding a clock having frequency information and phase information; a plurality of clock adjustor means for respectively generating clock signals having the same phases in response to the frequency information and phase information fed from said clock means; clocked devices receiving the clock signals; and means for maintaining delay times between said clock means and said clock signals of each clock adjustor means to be substantially equal, including feedback means responsive to said clock signals fed back from said clocked devices for producing feedback signals having a delay correlated to transmission delay of said clock signals, respectively for each of said clock adjustor means, and each of said clock adjustor means includes phase comparator means for detecting a phase difference between the clock and a respective one of said feedback signals and includes variable delay means for delaying the clock in accordance with said phase difference to produce a respective one of the clock signals; wherein said clock means feeds a reference clock having one frequency with said phase information and a different master clock having said frequency information with a frequency higher than said one frequency; wherein each of said clock adjustor means further includes a frequency divider for dividing the master clock which has been delayed by said variable delay means; wherein each of said variable delay means includes a plurality of delay circuits each responsive to said clock and producing respective output signals having different delay times, and a selector for selecting one of the outputs signals as the respective ones of said clock signals.

Claim 3

An integrated logical circuit according to claim 1, wherein each of said delay circuits has an emitter-follower circuit for generating a respective one of the output signals, and said emitter-follower circuit has means to compensate for delay time temperature-dependency.

Claim 4

An integrated logical circuit according to claim 2, wherein each of said delay circuits has a reference voltage source having a temperature coefficient and an emitter current source each connected to said emitter-follower circuit, said emitter current source including a bipolar transistor connected at its base to said reference voltage, and said means to compensate providing the emitter current source with a driving ability that is variable depending on the temperature coefficient.

Claim 5

An integrated logical circuit according to claim 3, wherein said temperature coefficient is positive.

Claim 6

A clock signal feed system comprising: means for feeding a clock including a phase information reference clock signal of one frequency; a plurality of PLL circuit means for generating respective slave output signals in response to said phase information reference clock signal, so that all of the slave output signals are in-phase and higher in frequency than the frequency of the phase information reference clock signal; and a plurality of optical fiber cables respectively coupled between said means for feeding a clock and each of said PLL circuit means for feeding said phase information reference clock signal to each of said PLL circuits.

Claim 7

A clock signal feed system comprising: means for feeding a clock including a phase information reference clock signal of one frequency; a plurality of PLL circuit means for generating respective slave output signals in response to said phase information reference clock signal, so that all of the slave output signals are in-phase and higher in frequency than the frequency of the phase information reference clock signal; and a plurality of optical fiber cables respectively coupled between said means for feeding a clock and each of said PLL circuit means for feeding said phase information reference clock signal to each of said PLL circuits.

Claim 8

A logic circuit comprising: a plurality of clocked devices at different physical locations throughout the circuit and each having a clock signal input; means for generating a clock having frequency information and phase information; a plurality of clock adjustor means at different locations throughout said circuit, each having a clock input and a slave clock output, for receiving said clock at said clock input and producing a corresponding slave clock at its slave clock output; first transmission line means between each of said slave clock outputs and a clock signal input for a corresponding one of said clocked devices; second transmission line means operatively connecting said means for generating a clock and each of said clock adjustor means for feeding the clock to the clock input of each of said clock adjustor means with a substantially equal clock delay; means providing a feedback signal to at least one of said clock adjustor means correlated to the slave clock delay between said one of said clock adjustor means and one of the clocked devices receiving the slave clock from said one of said clock adjustor means; said one of said clock adjustor means comparing said feedback signal with a reference and adjusting the delay of said slave clock in response to said comparison; said one of said clock adjustor means comparing said feedback signal with the phase information of said clock and shifting the phase of said slave clock in response to said comparison; each of said clock adjustor means being substantially identical to said one of said clock adjustor means and shifting its slave clock phase so that the phase relationship between its feedback signal and the clock is substantially identical to the same relationship for the other of said clock adjustor means; and said second transmission line means including transmission lines of equal length between each of said clock adjustor means and said means for generating a clock.

Claim 9

A logic circuit comprising: a plurality of clocked devices at different physical locations throughout the circuit and each having a clock signal input; means for generating a clock having frequency information and phase information; a plurality of clock adjustor means at different locations throughout said circuit, each having a clock input and a slave clock output, for receiving said clock at said clock input and producing a corresponding slave clock at its slave clock output; first transmission line means between each of said slave clock outputs and a clock signal input for a corresponding one of said clocked devices; second transmission line means operatively connecting said means for generating a clock and each of said clock adjustor means for feeding the clock to the clock input of each of said clock adjustor means with a substantially equal clock delay; means providing a feedback signal to at least one of said clock adjustor means correlated to the slave clock delay between said one of said clock adjustor means and one of the clocked devices receiving the slave clock from said one of said clock adjustor means; said one of said clock adjustor means comparing said feedback signal with a reference and adjusting the delay of said slave clock in response to said comparison; said one of said clock adjustor means comparing said feedback signal with the phase information of said clock and shifting the phase of said slave clock in response to said comparison; each of said clock adjustor means being substantially identical to said one of said clock adjustor means and shifting its slave clock phase so that the phase relationship between its feedback signal and the clock is substantially identical to the same relationship for the other of said clock adjustor means; and said second transmission line means including transmission lines of equal length between each of said clock adjustor means and said means for generating a clock.

Claim 10

The logic circuit according to claim 6, wherein each of said clock adjustor means includes a phase comparator comparing the phase of said clock and said feedback signal to produce a comparison signal, and variable delay means for producing a variable delay between said clock and said slave clock in response to said comparison signal.

Claim 11

The logic circuit according to claim 7, wherein each of said clock adjustor means further includes a frequency divider for reducing the frequency of said clock after passing through said variable delay means to provide a fixed frequency for said slave clock that is a whole number multiple of 2 less than the frequency of said clock; and said means for generating a clock producing said clock with a reference clock signal having the phase information and a separate master clock signal having the frequency information, so that said master clock has a frequency that is said whole number multiple of 2 greater than said clock having said phase information.

Claim 12

A logic circuit comprising: a plurality of clocked devices at different physical locations throughout the circuit and each having a clock signal input; means for generating a clock having frequency information and phase information; a plurality of clock adjustor means at different locations throughout said circuit, each having a clock input and a slave clock output, for receiving said clock at said clock input and producing a corresponding slave clock at its slave clock output; first transmission line means between each of said slave clock outputs and a clock signal input for a corresponding one of said clocked devices; second transmission line means operatively connecting said means for generating a clock and each of said clock adjustor means for feeding the clock to the clock input of each of said clock adjustor means with a substantially equal clock delay; means providing a feedback signal to at least one of said clock adjustor means correlated to the slave clock delay between said one of said clock adjustor means and one of the clocked devices receiving the slave clock from said one of said clock adjustor means; said one of said clock adjustor means comparing said feedback signal with a reference and adjusting the delay of said slave clock in response to said comparison; said means providing a feedback signal including third transmission line means having a delay substantially correlated to the slave clock delay of said first transmission line means for feeding the slave clock signal from its clocked device back to said one of said clock adjustor means with the delay correlated to the delay in said first transmission line means.

Claim 13

A logic circuit comprising: a plurality of clocked devices at different physical locations throughout the circuit and each having a clock signal input; means for generating a clock having frequency information and phase information; a plurality of clock adjustor means at different locations throughout said circuit, each having a clock input and a slave clock output, for receiving said clock at said clock input and producing a corresponding slave clock at its slave clock output; first transmission line means between each of said slave clock outputs and a clock signal input for a corresponding one of said clocked devices; second transmission line means operatively connecting said means for generating a clock and each of said clock adjustor means for feeding the clock to the clock input of each of said clock adjustor means with a substantially equal clock delay; means providing a feedback signal to at least one of said clock adjustor means correlated to the slave clock delay between said one of said clock adjustor means and one of the clocked devices receiving the slave clock from said one of said clock adjustor means; said one of said clock adjustor means comparing said feedback signal with a reference and adjusting the delay of said slave clock in response to said comparison; said means providing a feedback signal including third transmission line means having a delay substantially correlated to the slave clock delay of said first transmission line means for feeding the slave clock signal from its clocked device back to said one of said clock adjustor means with the delay correlated to the delay in said first transmission line means.

Claim 14

A logic circuit comprising: a plurality of clocked devices at different physical locations throughout the circuit and each having a clock signal input; means for generating a clock having frequency information and phase information; a plurality of clock adjustor means at different locations throughout said circuit, each having a clock input and a slave clock output, for receiving said clock at said clock input and producing a corresponding slave clock at its slave clock output; first transmission line means between each of said slave clock outputs and a clock signal input for a corresponding one of said clocked devices; second transmission line means operatively connecting said means for generating a clock and each of said clock adjustor means for feeding the clock to the clock input of each of said clock adjustor means with a substantially equal clock delay; means providing a feedback signal to at least one of said clock adjustor means correlated to the slave clock delay between said one of said clock adjustor means and one of the clocked devices receiving the slave clock from said one of said clock adjustor means; said one of said clock adjustor means comparing said feedback signal with a reference and adjusting the delay of said slave clock in response to said comparison; wherein there are a plurality of said means providing a feedback signal providing said feedback signal to respective ones of said clock adjustor means with a phase delay relative to said slave clock at said ones of said clock adjustor means output that has a fixed correlation to the delay in the slave clock between said ones of said clock adjustor means and their clocked devices, respectively which which fixed correlation is the same for each combination of clock adjustor means and clocked device; and wherein said second transmission lines means include transmission lines of equal length between each of said clock adjustor means and said means for generating a clock.

Claim 15

A logic circuit comprising: a plurality of clocked devices at different physical locations throughout the circuit and each having a clock signal input; means for generating a clock having frequency information and phase information; a plurality of clock adjustor means at different locations throughout said circuit, each having a clock input and a slave clock output, for receiving said clock at said clock input and producing a corresponding slave clock at its slave clock output; first transmission line means between each of said slave clock outputs and a clock signal input for a corresponding one of said clocked devices; second transmission line means operatively connecting said means for generating a clock and each of said clock adjustor means for feeding the clock to the clock input of each of said clock adjustor means with a substantially equal clock delay; means providing a feedback signal to at least one of said clock adjustor means correlated to the slave clock delay between said one of said clock adjustor means and one of the clocked devices receiving the slave clock from said one of said clock adjustor means; said one of said clock adjustor means comparing said feedback signal with a reference and adjusting the delay of said slave clock in response to said comparison; wherein there are a plurality of said means providing a feedback signal providing said feedback signal to respective ones of said clock adjustor means with a phase delay relative to said slave clock at said ones of said clock adjustor means output that has a fixed correlation to the delay in the slave clock between said ones of said clock adjustor means and their clocked devices, respectively which which fixed correlation is the same for each combination of clock adjustor means and clocked device; and wherein said second transmission lines means include transmission lines of equal length between each of said clock adjustor means and said means for generating a clock.

Claim 16

The logic circuit according to claim 10, wherein said ones of said clock adjustor include a phase comparator comparing the phase of said clock and said feedback signal to produce a comparison signal, and variable delay means for producing a variable delay between said clock and said slave clock in response to said comparison signal.

Claim 17

A logic circuit comprising: a plurality of clocked devices at different physical locations throughout the circuit and each having a clock signal input; means for generating a clock having frequency information and phase information; a plurality of clock adjustor means at different locations throughout said circuit, each having a clock input and a slave clock output, for receiving said clock at said clock input and producing a corresponding slave clock at its slave clock output; first transmission line means between each of said slave clock outputs and a clock signal input for a corresponding one of said clocked devices; second transmission line means operatively connecting said means for generating a clock and each of said clock adjustor means for feeding the clock to the clock input of each of said clock adjustor means with a substantially equal clock delay; means providing a feedback signal to at least one of said clock adjustor means correlated to the slave clock delay between said one of said clock adjustor means and one of the clocked devices receiving the slave clock from said one of said clock adjustor means; said one of said clock adjustor means comparing said feedback signal with a reference and adjusting the delay of said slave clock in response to said comparison; wherein said second transmission line means are optical fiber cables extending between said means for generating a clock and each of said clock adjustor means.

Claim 18

A logic circuit comprising: a plurality of clocked devices at different physical locations throughout the circuit and each having a clock signal input; means for generating a clock having frequency information and phase information; a plurality of clock adjustor means at different locations throughout said circuit, each having a clock input and a slave clock output, for receiving said clock at said clock input and producing a corresponding slave clock at its slave clock output; first transmission line means between each of said slave clock outputs and a clock signal input for a corresponding one of said clocked devices; second transmission line means operatively connecting said means for generating a clock and each of said clock adjustor means for feeding the clock to the clock input of each of said clock adjustor means with a substantially equal clock delay; means providing a feedback signal to at least one of said clock adjustor means correlated to the slave clock delay between said one of said clock adjustor means and one of the clocked devices receiving the slave clock from said one of said clock adjustor means; said one of said clock adjustor means comparing said feedback signal with a reference and adjusting the delay of said slave clock in response to said comparison; wherein said second transmission line means are optical fiber cables extending between said means for generating a clock and each of said clock adjustor means.

Claim 19

A logic circuit comprising: a plurality of clocked devices at different physical locations throughout the circuit and each having a clock signal input; means for generating a clock having frequency information and phase information; a plurality of clock adjustor means at different locations throughout said circuit, each having a clock input and a slave clock output, for receiving said clock at said clock input and producing a corresponding slave clock at its slave clock output; first transmission line means between each of said slave clock outputs and a clock signal input for a corresponding one of said clocked devices; second transmission line means operatively connecting said means for generating a clock and each of said clock adjustor means for feeding the clock to the clock input of each of said clock adjustor means with a substantially equal clock delay; means providing a feedback signal to at least one of said clock adjustor means correlated to the slave clock delay between said one of said clock adjustor means and one of the clocked devices receiving the slave clock from said one of said clock adjustor means; said one of said clock adjustor means comparing said feedback signal with a reference and adjusting the delay of said slave clock in response to said comparison; wherein each of said second transmission line means is of identical length; and said first transmission line means are of different lengths.

Claim 20

A logic circuit comprising: a plurality of clocked devices at different physical locations throughout the circuit and each having a clock signal input; means for generating a clock having frequency information and phase information; a plurality of clock adjustor means at different locations throughout said circuit, each having a clock input and a slave clock output, for receiving said clock at said clock input and producing a corresponding slave clock at its slave clock output; first transmission line means between each of said slave clock outputs and a clock signal input for a corresponding one of said clocked devices; second transmission line means operatively connecting said means for generating a clock and each of said clock adjustor means for feeding the clock to the clock input of each of said clock adjustor means with a substantially equal clock delay; means providing a feedback signal to at least one of said clock adjustor means correlated to the slave clock delay between said one of said clock adjustor means and one of the clocked devices receiving the slave clock from said one of said clock adjustor means; said one of said clock adjustor means comparing said feedback signal with a reference and adjusting the delay of said slave clock in response to said comparison; wherein each of said second transmission line means is of identical length; and said first transmission line means are of different lengths.

Claim 21

A logic circuit comprising: a plurality of clocked devices at different physical locations throughout the circuit and each having a clock signal input; means for generating a clock having frequency information and phase information; a plurality of clock adjustor means at different locations throughout said circuit, each having a clock input and a slave clock output, for receiving said clock at said clock input and producing a corresponding slave clock at its slave clock output; first transmission line means between each of said slave clock outputs and a clock signal input for a corresponding one of said clocked devices; second transmission line means operatively connecting said means for generating a clock and each of said clock adjustor means for feeding the clock to the clock input of each of said clock adjustor means with a substantially equal clock delay; means providing a feedback signal to at least one of said clock adjustor means correlated to the slave clock delay between said one of said clock adjustor means and one of the clocked devices receiving the slave clock from said one of said clock adjustor means; said one of said clock adjustor means comparing said feedback signal with a reference and adjusting the delay of said slave clock in response to said comparison; wherein said transmission line means include transmission lines of equal length between each of said clock adjustor means and said means for generating a clock.

Claim 22

A logic circuit comprising: a plurality of clocked devices at different physical locations throughout the circuit and each having a clock signal input; means for generating a clock having frequency information and phase information; a plurality of clock adjustor means at different locations throughout said circuit, each having a clock input and a slave clock output, for receiving said clock at said clock input and producing a corresponding slave clock at its slave clock output; first transmission line means between each of said slave clock outputs and a clock signal input for a corresponding one of said clocked devices; second transmission line means operatively connecting said means for generating a clock and each of said clock adjustor means for feeding the clock to the clock input of each of said clock adjustor means with a substantially equal clock delay; means providing a feedback signal to at least one of said clock adjustor means correlated to the slave clock delay between said one of said clock adjustor means and one of the clocked devices receiving the slave clock from said one of said clock adjustor means; said one of said clock adjustor means comparing said feedback signal with a reference and adjusting the delay of said slave clock in response to said comparison; wherein said transmission line means include transmission lines of equal length between each of said clock adjustor means and said means for generating a clock.

Claim 23

An integrated logical circuit comprising: clock means for feeding a clock having frequency information and phase information; a plurality of clock adjustor means for respectively generating clock signals having the same phases in response to the frequency information and phase information fed from said clock means; means for maintaining delay times between said clock means and said clock signals of each clock adjustor means to be substantially equal, including transmitting the clock from said clock means to each of said clock adjustor means with substantially equal delay times and providing the clock transmission length substantially equal between said clock means and each of said clock adjustor means.

Claim 24

An integrated logical circuit comprising: clock means for feeding a clock having frequency information and phase information; a plurality of clock adjustor means for respectively generating clock signals having the same phases in response to the frequency information and phase information fed from said clock means; means for maintaining delay times between said clock means and said clock signals of each clock adjustor means to be substantially equal, including transmitting the clock from said clock means to each of said clock adjustor means with substantially equal delay times and providing the clock transmission length substantially equal between said clock means and each of said clock adjustor means.

Claim 25

An integrated logical circuit according to claim 15, constructed entirely on a single chip.

Claim 26

An integrated logical circuit comprising: clock means for feeding a clock having frequency information and phase information; a plurality of clock adjustor means for respectively generating clock signals having the same phases in response to the frequency information and phase information fed from said clock means; means for maintaining delay times between said clock means and said clock signals of each clock adjustor means to be substantially equal, including transmitting the clock from said clock means to each of said clock adjustor means with substantially equal delay times and including the spacings between said clock means and each of said clock adjustor means being substantially equal.

Claim 27

An integrated logical circuit comprising: clock means for feeding a clock having frequency information and phase information; a plurality of clock adjustor means for respectively generating clock signals having the same phases in response to the frequency information and phase information fed from said clock means; means for maintaining delay times between said clock means and said clock signals of each clock adjustor means to be substantially equal, including transmitting the clock from said clock means to each of said clock adjustor means with substantially equal delay times and including the spacings between said clock means and each of said clock adjustor means being substantially equal.

Claim 28

An integrated logical circuit according to claim 17, constructed entirely on a single chip.

Claim 29

An integrated logical circuit comprising: clock means for feeding a clock having frequency information and phase information; a plurality of clock adjustor means for respectively generating clock signals having the same phases in response to the frequency information and phase information fed from said clock means; means for maintaining delay times between said clock means and said clock signals of each clock adjustor means to be substantially equal, including transmitting the clock from said clock means to each of said clock adjustor means with substantially equal delay times and including separate optical fibers transmitting the clock between said clock means and each of said clock adjustor means.

Claim 30

An integrated logical circuit comprising: clock means for feeding a clock having frequency information and phase information; a plurality of clock adjustor means for respectively generating clock signals having the same phases in response to the frequency information and phase information fed from said clock means; means for maintaining delay times between said clock means and said clock signals of each clock adjustor means to be substantially equal, including transmitting the clock from said clock means to each of said clock adjustor means with substantially equal delay times and including separate optical fibers transmitting the clock between said clock means and each of said clock adjustor means.

Claim 31

An integrated logical circuit according to claim 19, constructed entirely on a single chip.