Apparatus for synchronization of a first signal with a second signal

Claim 1

An apparatus for synchronizing a first signal with a second signal comprising: a plurality of delay means D i , where i goes from 1 to N and N is an integer, each delay means D i having an input I i and a delay output O i for delaying a signal received at the respective input I i by an increment δt of time and supplying the delayed signal at the respective delay output O i ; one delay means D 1 of the plurality delay means having an input I 1 connected to receive the first signal and each of the other delay means D i for i=2 to N being connected in series therewith; a plurality of latch means L i where i goes from 1 to N, connected in communication with the second signal and the plurality of delay outputs D i ; each latch means L i for latching the signal at the delay output O i respectively, in response to the second signal and for supplying the latched signal at latch output Q i , wherein a subset of the plurality of latch outputs Q i identify a characteristic of the first signal; means for detecting the characteristic of the first signal; and selecting means, responsive to the means for detecting the characteristic, for selecting at least one of the plurality of delay outputs O i and supplying the at least one selected delay output O i as essentially a phase-shifted copy of the first signal synchronized at the characteristic with the second signal.

Claim 2

An apparatus for synchronizing a first signal with a second signal comprising: a plurality of delay means D i , where i goes from 1 to N and N is an integer, each delay means D i having an input I i and a delay output O i for delaying a signal received at the respective input I i by an increment δt of time and supplying the delayed signal at the respective delay output O i ; one delay means D 1 of the plurality delay means having an input I 1 connected to receive the first signal and each of the other delay means D i for i=2 to N being connected in series therewith; a plurality of latch means L i where i goes from 1 to N, connected in communication with the second signal and the plurality of delay outputs D i ; each latch means L i for latching the signal at the delay output O i respectively, in response to the second signal and for supplying the latched signal at latch output Q i , wherein a subset of the plurality of latch outputs Q i identify a characteristic of the first signal; means for detecting the characteristic of the first signal; and selecting means, responsive to the means for detecting the characteristic, for selecting at least one of the plurality of delay outputs O i and supplying the at least one selected delay output O i as essentially a phase-shifted copy of the first signal synchronized at the characteristic with the second signal.

Claim 5

An apparatus for synchronizing a first signal with a second signal comprising: a plurality of delay means D i , where i goes from 1 to N and N is an integer, each delay means D i having an input I i and a delay output O i for delaying a signal received at the respective input I i by an increment δt of time and supplying the delayed signal at the respective delay output O i ; one delay means D 1 of said plurality of delay means having an input I 1 connected to receive the first signal and each of the other delay means D i for i=2 to N being connected in series therewith; a plurality of latch means L i where i goes from 1 to N, connected in communication with the second signal and the plurality of delay outputs O i , each latch means L i for latching the signal at the delay output O i , respectively, in response to the second signal and for supplying the latched signal at latch output Q i ; a plurality of gate means G i for i=1 to N, each gate means G i having a first input, a second input, and a third input, for generating a gate output equal to the third input when the first input is low and the second input is high; each gate means G i having its first input connected to latch output Q k , where k is an integer, its second input connected to receive latch output Q l where l is an integer, and its third input connected to delay output O j , where j is an integer; and output means, connected to receive the gate output of each of the plurality gate means G i for supplying essentially a phase-shifted copy of the first signal in synchronization with the second signal as an output signal.

Claim 6

An apparatus for synchronizing a first signal with a second signal comprising: a plurality of delay means D i , where i goes from 1 to N and N is an integer, each delay means D i having an input I i and a delay output O i for delaying a signal received at the respective input I i by an increment δt of time and supplying the delayed signal at the respective delay output O i ; one delay means D 1 of said plurality of delay means having an input I 1 connected to receive the first signal and each of the other delay means D i for i=2 to N being connected in series therewith; a plurality of latch means L i where i goes from 1 to N, connected in communication with the second signal and the plurality of delay outputs O i , each latch means L i for latching the signal at the delay output O i , respectively, in response to the second signal and for supplying the latched signal at latch output Q i ; a plurality of gate means G i for i=1 to N, each gate means G i having a first input, a second input, and a third input, for generating a gate output equal to the third input when the first input is low and the second input is high; each gate means G i having its first input connected to latch output Q k , where k is an integer, its second input connected to receive latch output Q l where l is an integer, and its third input connected to delay output O j , where j is an integer; and output means, connected to receive the gate output of each of the plurality gate means G i for supplying essentially a phase-shifted copy of the first signal in synchronization with the second signal as an output signal.