Computer system clock generator for generating tuned multiple clock signals

Claim 2

In a computer system, a computer system clock generator for generating a plurality of system clock signals comprising: an input clock for producing an input clock signal; a shift register ring having multiple shifting stages coupled at a first of at least two inputs to said input clock, said input clock signal controlling the shifting of said shifting stages; coupling means for coupling a second input of said shift register ring to a complemented version of one of a plurality of said shift register stages' output signals; and at least two tap selectors, each coupled to a plurality of said shifting stages for selectively combining signals output from said shift register ring stages to produce an output clock signal of desired characteristics, which output signals of said tap selectors vary when leaving said tap selectors in such a manner that they arrive in tune at predetermined locations in said computer system after having propagated along separate propagation paths; wherein said coupling means comprises a frequency controller coupled at its inputs to at least two of said shift register ring stages, said controller controlling the frequency of said output clock signals produced by selecting the shift register ring stage signal to be complemented and coupled to said second input.

Claim 3

In a computer system, a computer system clock generator for generating a plurality of system clock signals comprising: an input clock for producing an input clock signal; a shift register ring having multiple shifting stages coupled at a first of at least two inputs to said input clock, said input clock signal controlling the shifting of said shifting stages; coupling means for coupling a second input of said shift register ring to a complemented version of one of a plurality of said shift register stages' output signals; and at least two tap selectors, each coupled to a plurality of said shifting stages for selectively combining signals output from said shift register ring stages to produce an output clock signal of desired characteristics, including phase angle, which output signals of said tap selectors vary when leaving said tap selectors in such a manner that they arrive in tune at predetermined locations in said computer system after having propagated along separate propagation paths; wherein said coupling means comprises a frequency controller coupled at its inputs to at least two of said shift register ring stages, said controller controlling the frequency of said output clock signals produced by selecting the shift register ring stage signal to be complemented and coupled to said second input.

Claim 4

In a computer system, a computer system clock generator for generating a plurality of system clock signals comprising: an input clock for producing an input clock signal; a shift register ring having multiple shifting stages coupled at a first of at least two inputs to said input clock, said input clock signal controlling the shifting of said shifting stages; coupling means for coupling a second input of said shift register ring to a complemented version of one of a plurality of said shift register stages' output signals; and at least two tap selectors, each coupled to a plurality of said shifting stages for selectively combining signals output from said shift register ring stages to produce an output clock signal of desired characteristics, including phase angle, which output signals of said tap selectors vary when leaving said tap selectors in such a manner that they arrive in tune at predetermined locations in said computer system after having propagated along separate propagation paths; wherein said coupling means comprises a frequency controller coupled at its inputs to at least two of said shift register ring stages, said controller controlling the frequency of said output clock signals produced by selecting the shift register ring stage signal to be complemented and coupled to said second input.

Claim 5

In a computer system, a computer system clock generator for generating a plurality of system clock signals comprising: an input clock for producing an input clock signal; a shift register ring having multiple shifting stages coupled at a first of at least two inputs to said input clock, said input clock signal controlling the shifting of said shifting stages; coupling means for coupling a second input of said shift register ring to a complemented version of one of a plurality of said shift register stages' output signals; and at least two tap selectors, each coupled to a plurality of said shifting stages for selectively combining signals output from said shift register ring stages to produce an output clock signal of desired characteristics, including pulse width, which output signals of said tap selectors vary when leaving said tap selectors in such a manner that they arrive in tune at predetermined locations in said computer system after having propagated along separate propagation paths; wherein said coupling means comprises a frequency controller coupled at its inputs to at least two of said shift register ring stages, said controller controlling the frequency of said output clock signals produced by selecting the shift register ring stage signal to be complemented and coupled to said second input.

Claim 6

In a computer system, a computer system clock generator for generating a plurality of system clock signals comprising: an input clock for producing an input clock signal; a shift register ring having multiple shifting stages coupled at a first of at least two inputs to said input clock, said input clock signal controlling the shifting of said shifting stages; coupling means for coupling a second input of said shift register ring to a complemented version of one of a plurality of said shift register stages' output signals; and at least two tap selectors, each coupled to a plurality of said shifting stages for selectively combining signals output from said shift register ring stages to produce an output clock signal of desired characteristics, including pulse width, which output signals of said tap selectors vary when leaving said tap selectors in such a manner that they arrive in tune at predetermined locations in said computer system after having propagated along separate propagation paths; wherein said coupling means comprises a frequency controller coupled at its inputs to at least two of said shift register ring stages, said controller controlling the frequency of said output clock signals produced by selecting the shift register ring stage signal to be complemented and coupled to said second input.

Claim 7

In a computer system, a computer system clock generator for generating a plurality of system clock signals comprising: an input clock for producing an input clock signal; a shift register ring having multiple shifting stages coupled at a first of at least two inputs to said input clock, said input clock signal controlling the shifting of said shifting stages; coupling means for coupling a second input of said shift register ring to a complemented version of one of a plurality of said shift register stages' output signals; and at least two tap selectors, each coupled to a plurality of said shifting stages for selectively combining signals output from said shift register ring stages defining rising edges and falling edges, to produce an output clock signal of desired characteristics, which output signals of said tap selectors vary when leaving said tap selectors in such a manner that they arrive in tune at predetermined locations in said computer system after having propagated along separate propagation paths; wherein each said tap selector comprises a rising edge multiplexer means for selecting a rising edge and a falling edge multiplexer means for selecting a falling edge, and each said tap selector further comprises combining means coupled to said rising edge and falling edge multiplexer means for combining the outputs from said rising edge and falling edge multiplexer means to form said output clock signals.

Claim 8

In a computer system, a computer system clock generator for generating a plurality of system clock signals comprising: an input clock for producing an input clock signal; a shift register ring having multiple shifting stages coupled at a first of at least two inputs to said input clock, said input clock signal controlling the shifting of said shifting stages; coupling means for coupling a second input of said shift register ring to a complemented version of one of a plurality of said shift register stages' output signals; and at least two tap selectors, each coupled to a plurality of said shifting stages for selectively combining signals output from said shift register ring stages defining rising edges and falling edges, to produce an output clock signal of desired characteristics, which output signals of said tap selectors vary when leaving said tap selectors in such a manner that they arrive in tune at predetermined locations in said computer system after having propagated along separate propagation paths; wherein each said tap selector comprises a rising edge multiplexer means for selecting a rising edge and a falling edge multiplexer means for selecting a falling edge, and each said tap selector further comprises combining means coupled to said rising edge and falling edge multiplexer means for combining the outputs from said rising edge and falling edge multiplexer means to form said output clock signals.

Claim 9

The computer system clock generator in claim 4 further comprising control means for controlling in each tap selector, the operation of said rising and falling edge multiplexer means and said combining means.

Claim 10

The computer system clock generator in claim 5 wherein each said tap selector comprises separate delay means coupled between said rising edge multiplexer means and said combining means, and coupled between said falling edge multiplexer means and said combining means, for selectively delaying signals from said rising edge and falling edge multiplexer means under the control of said control means.

Claim 11

The computer system clock generator in claim 6 wherein said control means comprises in each tap selector, a control register coupled to said rising edge and falling edge multiplexer means, said combining means and said means for selectively delaying, for storing a control word, said control word directing the operation of of said rising edge and falling edge multiplexer means, said combining means and said means for selectively delaying.