US3577086A
Expired / Lapsed
US
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Generator of delayed sequences employing shift register techniques
Assignee: Individual
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Filing: 1968-09-30
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Granted: 1971-05-04
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Expires: 1988-09-30
Abstract
Abstract The circuitry involves a plurality of groups of shift register stages connected in cascade with temporary storage stages connected between each group of stages. A reference sequence is applied serially to the generator input and a number of substantially equally delayed replicas thereof are obtained from taps spaced along the generator, the number of the taps being different from the number of bits of the input reference sequence. In order to accomplish this, several different shift pulse trains must be applied to different of the groups of stages, the different shift pulse trains having different time delays or phases.
Inventors
- 👤 Ivan M Kliman
- 👤 Harold Smola
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:18
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/15093
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
131 words
A generator of respective groups of delayed reference digital signal sequences occurring at a prescribed reference sequence clock signal frequency comprising, a plurality of groups of shift register stages arranged in cascade, a temporary storage stage connected respectively between each of said groups of shift registers, means to apply said reference digital signal sequences serially to said generator, and means to obtain substantially equally delayed replicas of said reference digital signal sequences from respective taps connected to a prescribed stage of each of said groups of shift register stages, means to apply shifting pulses of the same frequency as the reference sequence clock signal rate to said generator, each succeeding group of stages having applied thereto shift pulse trains which are delayed relative to those of the preceding group of stages.
Claim 2
Dependent Claim
131 words
A generator of respective groups of delayed reference digital signal sequences occurring at a prescribed reference sequence clock signal frequency comprising, a plurality of groups of shift register stages arranged in cascade, a temporary storage stage connected respectively between each of said groups of shift registers, means to apply said reference digital signal sequences serially to said generator, and means to obtain substantially equally delayed replicas of said reference digital signal sequences from respective taps connected to a prescribed stage of each of said groups of shift register stages, means to apply shifting pulses of the same frequency as the reference sequence clock signal rate to said generator, each succeeding group of stages having applied thereto shift pulse trains which are delayed relative to those of the preceding group of stages.
Claim 3
Dependent Claim
69 words
The generator of claim 1 wherein said last-named means comprises a plurality of cascaded delay lines of equal length and having a single input terminal and respective output terminals for each of said delay lines, and means to apply said clock signal to said input terminal, said delayed shift pulse trains being obtained from said respective output terminals of each of said delay lines and across said input terminal.
Claim 4
Dependent Claim
39 words
The generator of claim 1 wherein said last-named means comprises a ring counter driven by said clock signal and having a plurality of prescribed output stages and wherein said delayed shift pulse trains are taken from said output stages.
Claim 5
Dependent Claim
81 words
The circuit of claim 1 wherein said generator comprises at least 14 of said groups of shift register stages and 15 of said temporary storage stages, and wherein each of said groups of reference digital signal sequences comprise 53 bits and wherein shifting pulse trains of five different phases or delays are applied to different of said groups of shift register stages, and wherein 50 substantially equally delayed replicas of said input reference digital signal sequences are obtained from said taps.
References Cited (Backward Citations)
US3108228A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-03 | 1974-11-02 | 1975-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-03 | 1978-11-02 | 1979-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-03 | 1982-11-02 | 1983-05-04 | $7700.00 | Window Closed / Lapsed |