US5073730A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current transient reduction for vlsi chips
Assignee: International Business Machines Corp
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Filing: 1990-04-23
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Granted: 1991-12-17
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Expires: 2010-04-23
Abstract
Abstract Described is a circuit arrangement for controlling peak transient current on data buses of VLSI chips. The circuit arrangement includes a phase lock loop (PLL) with a voltage control oscillator (VCO) made up of high speed inverter circuits that generate very short time interval pulses that are used to control the switching sequence of drivers onto the buses. As a result, the transients are distributed over a relatively short time interval and data throughput on the buses is not adversely affected.
Inventors
- 👤 Charles R. Hoffman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:38
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; G06F13/4077; H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0315
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
110 words
A VLSI chip comprising: a bus for transmitting data within a predetermined bus transfer cycle time; a plurality of driver modules, each one having an output node coupled to said bus; a plurality of logical AND gates, with each one coupled to each of the plurality of driver modules; a controller means coupled to the plurality of logical AND gates, said controller means generating gating pulses that sequence the AND gates so that output signals from said AND gates are presented sequentially to said driver modules whose use of the bus are spread over a time interval which is relatively short when compared to the predetermined bus transfer cycle time.
Claim 2
Dependent Claim
110 words
A VLSI chip comprising: a bus for transmitting data within a predetermined bus transfer cycle time; a plurality of driver modules, each one having an output node coupled to said bus; a plurality of logical AND gates, with each one coupled to each of the plurality of driver modules; a controller means coupled to the plurality of logical AND gates, said controller means generating gating pulses that sequence the AND gates so that output signals from said AND gates are presented sequentially to said driver modules whose use of the bus are spread over a time interval which is relatively short when compared to the predetermined bus transfer cycle time.
Claim 3
Dependent Claim
77 words
A VLSI chip comprising: a bus for transmitting data; a plurality of driver modules, each one having an output node coupled to said bus; and a controller means including a phase lock loop coupled to the driver modules, said controller means sequencing the switching of the driver modules in a controlled manner so that output signals from said driver modules are spread over a time interval which is relatively short when compared to the bus transfer cycle.
Claim 4
Dependent Claim
77 words
A VLSI chip comprising: a bus for transmitting data; a plurality of driver modules, each one having an output node coupled to said bus; and a controller means including a phase lock loop coupled to the driver modules, said controller means sequencing the switching of the driver modules in a controlled manner so that output signals from said driver modules are spread over a time interval which is relatively short when compared to the bus transfer cycle.
Claim 5
Dependent Claim
58 words
The VLSI chip of claim 2 wherein the phase lock loop includes a phase detector circuit means; a low pass filter circuit coupled to said phase detector circuit means; and a multi-stage ring VCO coupled to said low pass filter circuit with each stage of the multi-stage ring VCO controlling a selected one of the the driver modules.
Claim 6
Dependent Claim
22 words
The VLSI chip of claim 3 wherein each stage of the multistage ring VCO controls a selected group of the driver modules.
Claim 7
Dependent Claim
50 words
An improved integrated circuit arrangement comprising: a bus for transmitting data; a plurality of driver circuits coupled to the bus; and a phase locked loop coupled to said plurality of drivers, said phase locked loop generating a plurality of relatively closed spaced pulses that sequence the drivers onto the bus.
Claim 8
Dependent Claim
50 words
An improved integrated circuit arrangement comprising: a bus for transmitting data; a plurality of driver circuits coupled to the bus; and a phase locked loop coupled to said plurality of drivers, said phase locked loop generating a plurality of relatively closed spaced pulses that sequence the drivers onto the bus.
Claim 9
Dependent Claim
79 words
The improved integrated circuit arrangement of claim 5 wherein the phase locked loop includes a multi-stage VC ring oscillator; a low pass filter circuit coupled to an input of said VC ring oscillator; and a phase detector circuit having an output terminal coupled to the low pass filter circuit, an input terminal coupled to an input clock line and another input terminal coupled to a feedback conductor interconnecting an output terminal of the VC ring oscillator to its input.
Claim 10
Dependent Claim
27 words
The improved integrated circuit arrangement of claim 6 wherein the ring oscillator further includes means for adjusting the period of the VCO positioned in the feedback conductor.
Claim 11
Dependent Claim
16 words
The improved integrated circuit arrangement of claim 7 wherein the means includes a logic divide circuit.
Claim 12
Dependent Claim
22 words
The improved integrated circuit arrangement of claim 6 wherein the multi-stage VC ring oscillator includes a string of series connected inverter circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-16 | 1995-06-17 | 1995-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-16 | 1999-06-17 | 1999-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-16 | 2003-06-17 | 2003-12-17 | $7700.00 | Window Closed / Lapsed |