Abstract A circuit having a plurality of adding or ''''AND'''' circuit stages and a corresponding number of bistable state or ''''LATCH'''' circuit stages connected alternately in sequence to provide associated pairs. Each ''''LATCH'''' stage has in use a normal state in which it is inoperative and a triggered state in which an output connection of that stage provides one of a sequence of output signals, one input for the associated ''''AND'''' stage, and a changeover signal for an immediately adjacent ''''LATCH'''' stage. Additional inputs for the ''''AND'''' stages are provided from a connection or connections to which external control signals can be applied, and the application of two inputs to one of the ''''AND'''' stages produces an output thereof which acts to change over a corresponding one of the ''''LATCH'''' stages.
A sequence control circuit for providing a plurality of sequential output signals on sequence control circuit outputs only in response to a plurality of external control signals applied in turn to a plurality of sequence control circuit inputs comprising alternately positioned ''''AND'''' stage means and bistable latch stage means, each said bistable latch stage means having a normal stable state and an operative stable state wherein a latch output signal is provided and being operative to switch from the normal stable state to the operative stable state in response to a change over signal provided thereto by the next preceding ''''AND'''' stage means, and individual output means connected to each latch stage means to provide the latch output signal therefrom to a sequence control circuit output, said output means also operating to provide said latch output signal to the next following ''''AND'''' stage means and to the said bistable preceding latch stage means, said last preceding latch stage means being reset to the normal stable state by said latch output signal, each said ''''AND'''' stage means being connected to receive an external control signal from one of said sequence control signal inputs and operating upon the simultaneous reception of an external control signal and a latch output signal from the next preceding latch stage means to provide a change over signal to the next following latch stage means.
Claim 2
Dependent Claim
228 words
A sequence control circuit for providing a plurality of sequential output signals on sequence control circuit outputs only in response to a plurality of external control signals applied in turn to a plurality of sequence control circuit inputs comprising alternately positioned ''''AND'''' stage means and bistable latch stage means, each said bistable latch stage means having a normal stable state and an operative stable state wherein a latch output signal is provided and being operative to switch from the normal stable state to the operative stable state in response to a change over signal provided thereto by the next preceding ''''AND'''' stage means, and individual output means connected to each latch stage means to provide the latch output signal therefrom to a sequence control circuit output, said output means also operating to provide said latch output signal to the next following ''''AND'''' stage means and to the said bistable preceding latch stage means, said last preceding latch stage means being reset to the normal stable state by said latch output signal, each said ''''AND'''' stage means being connected to receive an external control signal from one of said sequence control signal inputs and operating upon the simultaneous reception of an external control signal and a latch output signal from the next preceding latch stage means to provide a change over signal to the next following latch stage means.