Plural stage selector system including "not" and "and-not" circuits in each stage thereof

Claim 1

IN COMBINATION IN A PREFERENTIAL SELECTOR SYSTEM, A PLURALITY OF STAGES ARRANGED IN ORDER OF PREFERENCE IN A LINEAR ARRAY, MEANS FOR SIMULTANEOUSLY APPLYING RESPECTIVE INPUT SIGNALS TO SAID STAGES, A SOURCE OF SERIAL "O" TIMING SIGNALS, EACH STAGE INCLUDING FIRST MEANS RESPONSIVE TO A "1" INPUT SIGNAL APPLIED THERETO FOR PROVIDING AN INHIBITING SIGNAL, SAID FIRST MEANS OF EACH STAGE BEING ALSO RESPONSIVE TO AN INHIBITING SIGNAL FROM AN ADJACENT HIGHERORDERED STAGE FOR PROVIDING SAID INHIBITING SIGNAL, SAID FIRST MEANS IN EACH STAGE INCLUDING A FIRST AND-NOT CIRCUIT HAVING INPUT AND OUTPUT TERMINALS AND A NOT CIRCUIT HAVING A SINGLE INPUT TERMINAL CONNECTED TO THE OUTPUT TERMINAL OF SAID FIRST AND-NOT CIRCUIT, SAID NOT CIRCUIT IN EACH STAGE EXCEPT THE LOWEST-ORDERED STAGE OF SAID ARRAY HAVING A SINGLE OUTPUT TERMINAL CONNECTED TO AN INPUT TERMINAL OF THE FIRST AND-NOT CIRCUIT IN THE ADJACENT LOWER-ORDERED STAGE OF SAID ARRAY FOR SUPPLYING AN INHIBITING SIGNAL TO SAID FIRST AND-NOT CIRCUIT, SAID MEANS FOR APPLYING INPUT SIGNALS INCLUDING AN INPUT REGISTER HAVING A PLURALITY OF BISTABLE CIRCUITS WHOSE OUTPUT TERMINALS ARE RESPECTIVELY CONNECTED TO THE INPUT TERMINALS OF SAID FIRST AND-NOT CIRCUITS IN SAID STAGES, EACH STAGE INCLUDING SECOND MEANS RESPONSIVE TO THE SIMULTANEOUS OCCURRENCE OF (1) A TIMING SIGNAL (2) A CONTROL SIGNAL FROM SAID FIRST MEANS INDICATIVE OF A "1" INPUT SIGNAL AND (3) THE ABSENCE OF AN INHIBITING SIGNAL FROM A HIGHERORDERED STAGE FOR PROVIDING A "1" OUTPUT SIGNAL, AND THIRD MEANS RESPONSIVE TO THE APPEARANCE OF A "1" SIGNAL AT THE OUTPUT OF A STAGE FOR CAUSING THE INPUT SIGNAL APPLIED TO THE STAGE TO BE CHANGED TO A "0" INDICATION AND FOR CAUSING THE "1" OUTPUT SIGNAL AND THE INHIBITING SIGNAL FROM THE STAGE TO PERSIST FOR THE DURATION OF THE TIMING SIGNAL.