US5570045A
Expired / Lapsed
US
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Hierarchical clock distribution system and method
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1995-06-07
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Granted: 1996-10-29
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Expires: 2015-06-07
Abstract
Abstract A microelectronic circuit includes a plurality of circuitry blocks and sub-blocks, a clock driver, an electrical interconnect that directly connects the clock driver to the sub-blocks, and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively. A method of producing a hierarchial clock distribution system for the circuit includes determining clock skews between the clock driver and the sub-blocks respectively. Delay buffers are selected from a predetermined set of delay buffers having the same physical size and different delays, with the delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively. Each delay buffer includes a delay line, and a number of loading elements that are connected to the delay line, with the number of loading elements being selected to provide the required clock delay for the respective sub-block.
Inventors
- 👤 Apo C. Erdal
- 👤 Trung Nguyen
- 👤 Kwok M. Yue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:27
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/394; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
97 words
A hierarchial clock distribution system for a microelectronic circuit including a plurality of circuitry blocks and sub-blocks, comprising: a clock driver; delay buffers provided in the sub-blocks respectively; an electrical interconnect that directly connects the clock driver to the delay buffers; and balanced clock-tree distribution systems provided between the delay buffers and circuitry in the sub-blocks respectively; the delay buffers providing equal clock skews from the clock driver to the distribution systems respectively, in which: the delay buffers have the same physical size, and comprise identical delay lines that are loaded to equalize said clock skews respectively.
Claim 2
Dependent Claim
97 words
A hierarchial clock distribution system for a microelectronic circuit including a plurality of circuitry blocks and sub-blocks, comprising: a clock driver; delay buffers provided in the sub-blocks respectively; an electrical interconnect that directly connects the clock driver to the delay buffers; and balanced clock-tree distribution systems provided between the delay buffers and circuitry in the sub-blocks respectively; the delay buffers providing equal clock skews from the clock driver to the distribution systems respectively, in which: the delay buffers have the same physical size, and comprise identical delay lines that are loaded to equalize said clock skews respectively.
Claim 3
Dependent Claim
24 words
A system as in claim 1, in which the delay lines are loaded by numbers of loading elements that equalize said clock skews respectively.
Claim 4
Dependent Claim
28 words
A system as in claim 2, in which: the delay lines comprise strings of logic elements; and the loading elements are connected to outputs of the logic elements.
Claim 5
Dependent Claim
13 words
A system as in claim 3, in which the logic elements comprises inverters.
Claim 6
Dependent Claim
33 words
A system as in claim 3, in which the loading elements comprise field-effect transistors having gates connected to outputs of the logic elements, and sources and drains connected to a constant electrical potential.
Claim 7
Dependent Claim
84 words
A system as in claim 3, in which each loading element comprises: a PMOS field-effect transistor having a gate connected to an output of one of the logic elements, and a source and a drain connected to a first constant electrical potential; and an NMOS field-effect transistor having a gate connected to an output of said one of said logic elements, and a source and a drain connected to a second constant electrical potential that is negative relative to the first constant electrical potential.
Claim 8
Dependent Claim
32 words
A system as in claim 3, in which each logic element has a number n of loading elements connected to the output thereof, where 0≦n≦N, and N is a predetermined maximum value.
Claim 9
Dependent Claim
83 words
A clock delay buffer for a microelectronic circuit, comprising: a delay line; and a number of loading elements that are connected to the delay line, said number being selected to provide a predetermined clock delay, in which: the delay line comprises a string of logic elements; the loading elements are connected to outputs of the logic elements; and the loading elements comprise field-effect transistors having gates connected to outputs of the logic elements, and sources and drains connected to a constant electrical potential.
Claim 10
Dependent Claim
83 words
A clock delay buffer for a microelectronic circuit, comprising: a delay line; and a number of loading elements that are connected to the delay line, said number being selected to provide a predetermined clock delay, in which: the delay line comprises a string of logic elements; the loading elements are connected to outputs of the logic elements; and the loading elements comprise field-effect transistors having gates connected to outputs of the logic elements, and sources and drains connected to a constant electrical potential.
Claim 11
Dependent Claim
134 words
A clock delay buffer for a microelectronic circuit, comprising: a delay line; and a number of loading elements that are connected to the delay line, said number being selected to provide a predetermined clock delay, in which: the delay line comprises a string of logic elements; the loading elements are connected to outputs of the logic elements; and each loading element comprises: a PMOS field-effect transistor having a gate connected to an output of one of the logic elements, and a source and a drain connected to a first constant electrical potential; and an NMOS field-effect transistor having a gate connected to an output of said one of said logic elements, and a source and a drain connected to a second constant electrical potential that is negative relative to the first constant electrical potential.
Claim 12
Dependent Claim
134 words
A clock delay buffer for a microelectronic circuit, comprising: a delay line; and a number of loading elements that are connected to the delay line, said number being selected to provide a predetermined clock delay, in which: the delay line comprises a string of logic elements; the loading elements are connected to outputs of the logic elements; and each loading element comprises: a PMOS field-effect transistor having a gate connected to an output of one of the logic elements, and a source and a drain connected to a first constant electrical potential; and an NMOS field-effect transistor having a gate connected to an output of said one of said logic elements, and a source and a drain connected to a second constant electrical potential that is negative relative to the first constant electrical potential.
Claim 13
Dependent Claim
82 words
A clock delay buffer for a microelectronic circuit, comprising: a delay line; and a number of loading elements that are connected to the delay line, said number being selected to provide a predetermined clock delay, in which: the delay line comprises a string of logic elements; the loading elements are connected to outputs of the logic elements; and each logic element has a number n of loading elements connected to the output thereof, where 0≦n≦N, and N is a predetermined maximum value.
Claim 14
Dependent Claim
82 words
A clock delay buffer for a microelectronic circuit, comprising: a delay line; and a number of loading elements that are connected to the delay line, said number being selected to provide a predetermined clock delay, in which: the delay line comprises a string of logic elements; the loading elements are connected to outputs of the logic elements; and each logic element has a number n of loading elements connected to the output thereof, where 0≦n≦N, and N is a predetermined maximum value.
Claim 15
Independent Claim
133 words
A method of producing a hierarchial clock distribution system for a microelectronic circuit, in which: the microelectronic circuit comprises: a plurality of circuitry blocks and sub-blocks: a clock driver; an electrical interconnect that directly connects the clock driver to the sub-blocks; and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively; the method comprising the steps of: (a) determining clock skews between the clock driver and the sub-blocks respectively; (b) selecting delay buffers from a predetermined set of delay buffers having a same physical size and different delays, said selected delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively; and (c) inserting said selected delay buffers in the sub-blocks between the electrical interconnect and the distribution systems respectively.
Claim 16
Independent Claim
133 words
A method of producing a hierarchial clock distribution system for a microelectronic circuit, in which: the microelectronic circuit comprises: a plurality of circuitry blocks and sub-blocks: a clock driver; an electrical interconnect that directly connects the clock driver to the sub-blocks; and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively; the method comprising the steps of: (a) determining clock skews between the clock driver and the sub-blocks respectively; (b) selecting delay buffers from a predetermined set of delay buffers having a same physical size and different delays, said selected delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively; and (c) inserting said selected delay buffers in the sub-blocks between the electrical interconnect and the distribution systems respectively.
Claim 17
Independent Claim
170 words
A method of producing a hierarchial clock distribution system for a microelectronic circuit, in which: the microelectronic circuit comprises: a plurality of circuitry blocks and sub-blocks: a clock driver; an electrical interconnect that directly connects the clock driver to the sub-blocks; and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively; the method comprising the steps of: (a) determining clock skews between the clock driver and the sub-blocks respectively; (b) selecting delay buffers from a predetermined set of delay buffers having a same physical size and different delays, said selected delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively; and (c) inserting said selected delay buffers in the sub-blocks between the electrical interconnect and the distribution systems respectively, in which: the delay buffers of said set comprise identical delay lines that are loaded differently to provide said different delays respectively; and step (b) comprises selecting said selected delay buffers in accordance with said loadings respectively.
Claim 18
Independent Claim
170 words
A method of producing a hierarchial clock distribution system for a microelectronic circuit, in which: the microelectronic circuit comprises: a plurality of circuitry blocks and sub-blocks: a clock driver; an electrical interconnect that directly connects the clock driver to the sub-blocks; and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively; the method comprising the steps of: (a) determining clock skews between the clock driver and the sub-blocks respectively; (b) selecting delay buffers from a predetermined set of delay buffers having a same physical size and different delays, said selected delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively; and (c) inserting said selected delay buffers in the sub-blocks between the electrical interconnect and the distribution systems respectively, in which: the delay buffers of said set comprise identical delay lines that are loaded differently to provide said different delays respectively; and step (b) comprises selecting said selected delay buffers in accordance with said loadings respectively.
Claim 19
Independent Claim
158 words
A method of producing a hierarchial clock distribution system for a microelectronic circuit in which: the microelectronic circuit comprises: a plurality of circuitry blocks and sub-blocks: a clock driver; an electrical interconnect that directly connects the clock driver to the sub-blocks; and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively; the method comprising the steps of: (a) determining clock skews between the clock driver and the sub-blocks respectively; (b) selecting delay buffers from a predetermined set of delay buffers having a same physical size and different delays, said selected delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively; and (c) inserting said selected delay buffers in the sub-blocks between the electrical interconnect and the distribution systems respectively, in which: step (a) comprises performing a timing analysis of the microelectronic circuit with the delay buffers all providing a minimum value of clock skew.
Claim 20
Independent Claim
158 words
A method of producing a hierarchial clock distribution system for a microelectronic circuit in which: the microelectronic circuit comprises: a plurality of circuitry blocks and sub-blocks: a clock driver; an electrical interconnect that directly connects the clock driver to the sub-blocks; and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively; the method comprising the steps of: (a) determining clock skews between the clock driver and the sub-blocks respectively; (b) selecting delay buffers from a predetermined set of delay buffers having a same physical size and different delays, said selected delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively; and (c) inserting said selected delay buffers in the sub-blocks between the electrical interconnect and the distribution systems respectively, in which: step (a) comprises performing a timing analysis of the microelectronic circuit with the delay buffers all providing a minimum value of clock skew.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-29 | 2000-04-29 | 2000-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-29 | 2004-04-29 | 2004-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-29 | 2008-04-29 | 2008-10-29 | $7700.00 | Window Closed / Lapsed |